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CD74HCT573

ACTIVE

High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs

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Data sheet

CD74HCT573

ACTIVE
Data sheet Order now

Product details

Number of channels 8 Technology family HCT Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 25 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Features Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
Number of channels 8 Technology family HCT Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 25 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Features Balanced outputs, Flow-through pinout, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Catalog
PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm) SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) SSOP (DB) 20 56.16 mm² (7.2 mm × 7.8 mm)
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet CDx4HCT573 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. E) PDF | HTML Jun 30, 2022
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Supported products & hardware
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Package Pins CAD symbols, footprints & 3D models
PDIP (N) 20 Ultra Librarian
SOIC (DW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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