DRA821U-Q1

ACTIVO

Detalles del producto

CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 4 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Features Networking Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 4 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Features Networking Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ALM) 433 295.84 mm² (17.2 mm × 17.2 mm)

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0GHz with optional lockstep operation
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA
  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1
  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0GHz
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0GHz with optional lockstep operation
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA
  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1
  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos DRA821 Jacinto™ Processors datasheet (Rev. F) PDF | HTML 9/06/2026
* Guía del usuario J7200 DRA821 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. D) PDF | HTML 16/12/2024
* Errata J7200 DRA821 Silicon Revision 1.0, 2.0 (Rev. F) PDF | HTML 2/06/2026
Información sobre seguridad funcional Jacinto Functional Safety Enablers (Rev. B) PDF | HTML 5/11/2026
Nota sobre la aplicación A Guide to USB2.0 High Speed Host TX Electrical Compliance PDF | HTML 25/09/2026
Nota sobre la aplicación Keywriter Deployment Strategies: Secure Device Provisioning in Production Environments PDF | HTML 26/08/2026
Nota sobre la aplicación QSPI Addressing Mode Considerations for AM62Ax Devices PDF | HTML 20/08/2026
Nota sobre la aplicación DDR Inline ECC Error Address Decoding on Jacinto™ 7 and Sitara™ Processors PDF | HTML 20/08/2026
Nota sobre la aplicación OSPI and QSPI Flash Integration Guide for TDA4x Devices PDF | HTML 19/08/2026
Nota sobre la aplicación DDR Inline ECC Error Injection and Validation Guide for Jacinto™ 7 and Sitara™ Processors PDF | HTML 19/08/2026
Nota sobre la aplicación A Guide to USB3.0 Gen1 SuperSpeed Host Transmit Electrical Compliance PDF | HTML 6/08/2026
Guía de diseño J7200 DRA821 Power-Supply Design Using the TPS6594-Q1 (Rev. A) PDF | HTML 10/07/2026
Información sobre seguridad funcional Confirmation of Software Component Qualification for JACINTO IPC for J721E, J721S2, J7200, J784S4, and J742S2 PDF | HTML 19/03/2026
Nota sobre la aplicación Boot Flow Options on TDA4 Devices PDF | HTML 5/01/2026
Información sobre seguridad funcional J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 1/10/2025
Información sobre seguridad funcional J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 25/09/2025
Información sobre seguridad funcional J721E, J721S2, J7200, J722S, J742S2, J784S4 MCAL TÜV SÜD Functional Safety Certificate (Rev. A) 25/09/2025
Información sobre seguridad funcional TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17/06/2025
Informe Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26/02/2025
Informe Software-Defined Vehicles Shift the Future of Automotive Electronics Into Gear (Rev. B) PDF | HTML 21/01/2025
Nota sobre la aplicación Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 5/08/2024
Nota sobre la aplicación Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 4/06/2024
Nota sobre la aplicación MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14/05/2024
Nota sobre la aplicación Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 4/04/2024
Nota sobre la aplicación Jacinto7 HS Device Customer Return Process PDF | HTML 16/11/2023
Nota sobre la aplicación Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15/11/2023
Nota sobre la aplicación UART Log Debug System on Jacinto 7 SoC PDF | HTML 9/01/2023
Guía del usuario Powering DRA821 with TPS6594-Q1 and LP8764-Q1 (Rev. A) PDF | HTML 12/09/2022
Nota sobre la aplicación How to Linux Fast Boot on DRA821U (Rev. A) PDF | HTML 28/07/2022
Nota sobre la aplicación Dual-TDA4x System Solution PDF | HTML 29/04/2022
Nota sobre la aplicación SPI Enablement & Validation on TDA4 Family PDF | HTML 5/04/2022
Nota sobre la aplicación Enabling MAC2MAC Feature on Jacinto7 Soc 10/01/2022
Más documentación Jacinto™ 7 automotive processors 14/12/2021
Nota sobre la aplicación Jacinto 7 Thermal Management Guide - Software Strategies PDF | HTML 10/12/2021
Nota sobre la aplicación Jacinto 7 Display Subsystem Overview PDF | HTML 10/12/2021
Información sobre seguridad funcional Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13/10/2021
Nota sobre la aplicación TISCI Server Integration in Vector AUTOSAR PDF | HTML 16/07/2021
Nota sobre la aplicación TDA4 Flashing Techniques PDF | HTML 8/07/2021
Nota sobre la aplicación J721E DDR Firewall Example PDF | HTML 1/07/2021
Información sobre seguridad funcional Build safer, efficient, intelligent and autonomous robots 4/03/2021
Informe Security Enablers on Jacinto™ 7 Processors 4/01/2021
Informe Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22/10/2020
Informe Evolving automotive gateways for next-generation vehicles (Rev. B) 9/10/2020
Nota sobre la aplicación OSPI Tuning Procedure PDF | HTML 8/07/2020

Diseño y desarrollo

Soluciones de alimentación

Busque las soluciones de alimentación disponibles para el DRA821U-Q1. TI ofrece soluciones de alimentación para sistemas en chip (SoC), procesadores, microcontroladores, sensores y matrices de compuertas programables de campo (FPGA), sean o no de TI.

Placa de evaluación

J7200XSOMXEVM — Sistema en módulo DRA821

The J7200XSOMG01EVM system-on-module—when paired with the J721EXCP01EVM common processor board—lets you evaluate the DRA821 processor for networking applications throughout automotive and industrial markets. These processors perform particularly well in industrial and automotive gateway (...)

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Guía del usuario: PDF | HTML
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Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

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Sonda de depuración

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El XDS560v2 es el modelo de mayor rendimiento de la familia de sondas de depuración XDS560™ y es compatible tanto con el estándar JTAG tradicional (IEEE 1149.1) como con cJTAG (IEEE 1149.7).  Tenga en cuenta que no es compatible con la depuración por cable serie (SWD).

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Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)

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El kit de calificación de compiladores de TI se desarrolló para ayudar a los clientes a calificar el uso del compiladores C/C++ ARM®, C28/CLA, C29, C6000™ o C7000™ de TI respecto de normas de seguridad funcional y ciberseguridad. 

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Pedidos y calidad

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