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SN74HCT540

ACTIVE

8-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs and 3-state outputs

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Data sheet

SN74HCT540

ACTIVE
Data sheet Order now

Product details

Technology family HCT Number of channels 8 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family HCT Number of channels 8 IOL (max) (mA) 6 IOH (max) (mA) -6 Supply current (max) (µA) 80 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Input clamp diode, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm² (12.8 mm × 10.3 mm) PDIP (N) 20 228.702 mm² (24.33 mm × 9.4 mm)
  • Operating Voltage Range of 4.5 V to 5.5 V
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
  • Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)
  • Operating Voltage Range of 4.5 V to 5.5 V
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 12 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Inputs Are TTL-Voltage Compatible
  • High-Current 3-State Outputs Interface Directly With System Bus or Can Drive Up To 15 LSTTL Loads
  • Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs)

These octal buffers and line drivers are designed to have the performance of the ’HCT240 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.

The 3-state control gate is a 2-input NOR. If either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state. The ’HCT540 devices provide inverted data at the outputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These octal buffers and line drivers are designed to have the performance of the ’HCT240 devices and a pinout with inputs and outputs on opposite sides of the package. This arrangement greatly facilitates printed circuit board layout.

The 3-state control gate is a 2-input NOR. If either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state. The ’HCT540 devices provide inverted data at the outputs.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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CD74ACT540 ACTIVE 8-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs and 3-state outputs Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

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* Data sheet SN54HCT540, SN74HCT540 datasheet (Rev. C) Mar 18, 2003

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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Simulation model

SN74HCT540 Behavioral SPICE Model

SCLM196.ZIP (7 KB) - PSpice model
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SOIC (DW) 20 Ultra Librarian
PDIP (N) 20 Ultra Librarian
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