DP83TC817-Q1-DESIGN — DP83TC817-Q1 100BASE-T1 PHY with MACsec
Supported products & hardware
Products
Ethernet PHYs
- DP83TC817S-Q1 — Automotive 100BASE-T1 Ethernet PHY with MACsec, precise time synchronization and TC-10
The DP83TC817S-Q1 is an IEEE 802.3bw and Open Alliance (OA) compliant automotive qualified 100Base-T1 Ethernet physical layer transceiver. The device provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables with xMII interface flexibility.
The DP83TC817S-Q1 integrates IEEE 802.1AE line rate security with authentication and optional encryption support to secure communication over the network. The PHY supports up to 16 secure association (SA) channels with automatic SAK rollover and extended packet numbering support. DP83TC817S-Q1 offers ingress classification to filter the unwanted packets & supports WAN MACsec for end-to-end security.
The DP83TC817S-Q1 integrates IEEE802.1AS / IEEE1588v2 to enable highly accurate time synchronization and hardware time stamping for time-sensitive, real-time controlled applications, with support for encrypted PTP packets.
The DP83TC817S-Q1 supports OA TC-10 low power sleep feature with wake forwarding for reduced system power consumption when communication is not required.
The DP83TC817S-Q1 is footprint compatible to TIs 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with a single board for different speeds and features.
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| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
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