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DLPC2607

NOT RECOMMENDED FOR NEW DESIGNS

DLP® display controller for DLP2000 (0.2 nHD) DMD

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Data sheet

DLPC2607

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

Component type Display Controller Display resolution (max) nHD (640x360) System brightness (max) (lm) 50 Chipset family DLP2000, DLPA1000 Input frame rate (max) (Hz) 60 Rating Catalog Video ports 24-bit RGB, BT656, Parallel Operating temperature range (°C) -30 to 85
Component type Display Controller Display resolution (max) nHD (640x360) System brightness (max) (lm) 50 Chipset family DLP2000, DLPA1000 Input frame rate (max) (Hz) 60 Rating Catalog Video ports 24-bit RGB, BT656, Parallel Operating temperature range (°C) -30 to 85
NFBGA (ZVB) 176 49 mm² 7 x 7
  • Supports Reliable Operation of the 0.2-nHD,
    0.24-VGA, and 0.3-WVGA DMDs
  • Multi-Mode, 24-Bit Input Pixel Interfaces:
    • Supports Parallel or BT656 Bus Protocol
    • Supports Input Sizes from QVGA Through WVGA
    • Supports 1- to 60-Hz Frame Rates
    • Supports Pixel Clock up to 33.5 MHz
    • Supports Landscape and Portrait Orientations
    • Support 8-, 16-, 18-, and 24-Bit Bus Options
    • Supports 3 Input Color Bit-Depth Options:
      • RGB888, YCrCb888
      • RGB666, YCrCb666
      • RGB565, 4:2:2 YCrCb
  • Pixel Data Processing:
    • Image Resizing (Scaling)
    • Frame Rate Conversion
    • Color Coordinate Adjustment
    • Automatic Gain Control
    • Programmable Degamma
    • Spatial-Temporal Multiplexing (Dithering)
    • Video Processing Support:
      • Color Space Conversion
      • 4:2:2 to 4:4:4 Chroma Interpolation
      • Field Scaled De-Interlacing
  • Packaged in a 176-Pin, 0.4-mm Pitch, VFBGA
  • External Memory Support:
    • 166-MHz Mobile DDR SDRAM
    • 33.3-MHz Serial Flash
  • WVGA, VGA, and nHD DMD Display Support
    • DMD Bit-Plane Generation and Formatting
    • Programmable Bit-Plane Display Sequencer (Controls the LED Enables and DMD Loading)
    • 76.2-MHz Double Data Rate (DDR) DMD I/F
    • Pulse-Width Modulation (PWM) for Mirrors:
      • Auto DMD Parking at Power-Down
      • 24-Bit Bit-Depth on DMD
  • System Control:
    • I2C Control of Device Configuration
    • Programmable Splash Screens
    • Programmable LED Current Control
    • DMD Power and Mirror Driver Control
    • DMD Horizontal and Vertical Display Image Flip
    • Display Image Rotation
    • Flash-Based Configuration Batch Files
    • I/F Sleep Still Image Power Savings Mode
  • Test Support:
    • Built-In Test Pattern Generation
    • JTAG With Boundary Scan Test Support
  • Supports Reliable Operation of the 0.2-nHD,
    0.24-VGA, and 0.3-WVGA DMDs
  • Multi-Mode, 24-Bit Input Pixel Interfaces:
    • Supports Parallel or BT656 Bus Protocol
    • Supports Input Sizes from QVGA Through WVGA
    • Supports 1- to 60-Hz Frame Rates
    • Supports Pixel Clock up to 33.5 MHz
    • Supports Landscape and Portrait Orientations
    • Support 8-, 16-, 18-, and 24-Bit Bus Options
    • Supports 3 Input Color Bit-Depth Options:
      • RGB888, YCrCb888
      • RGB666, YCrCb666
      • RGB565, 4:2:2 YCrCb
  • Pixel Data Processing:
    • Image Resizing (Scaling)
    • Frame Rate Conversion
    • Color Coordinate Adjustment
    • Automatic Gain Control
    • Programmable Degamma
    • Spatial-Temporal Multiplexing (Dithering)
    • Video Processing Support:
      • Color Space Conversion
      • 4:2:2 to 4:4:4 Chroma Interpolation
      • Field Scaled De-Interlacing
  • Packaged in a 176-Pin, 0.4-mm Pitch, VFBGA
  • External Memory Support:
    • 166-MHz Mobile DDR SDRAM
    • 33.3-MHz Serial Flash
  • WVGA, VGA, and nHD DMD Display Support
    • DMD Bit-Plane Generation and Formatting
    • Programmable Bit-Plane Display Sequencer (Controls the LED Enables and DMD Loading)
    • 76.2-MHz Double Data Rate (DDR) DMD I/F
    • Pulse-Width Modulation (PWM) for Mirrors:
      • Auto DMD Parking at Power-Down
      • 24-Bit Bit-Depth on DMD
  • System Control:
    • I2C Control of Device Configuration
    • Programmable Splash Screens
    • Programmable LED Current Control
    • DMD Power and Mirror Driver Control
    • DMD Horizontal and Vertical Display Image Flip
    • Display Image Rotation
    • Flash-Based Configuration Batch Files
    • I/F Sleep Still Image Power Savings Mode
  • Test Support:
    • Built-In Test Pattern Generation
    • JTAG With Boundary Scan Test Support

The DLPC2607 is a low power DLP™ digital controller for battery powered display applications. The controller supports reliable operation of 0.3-WVGA, 0.24-VGA and 0.2-nHD DMDs. The DLPC2607 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and low power displays.

The DLPC2607 is a low power DLP™ digital controller for battery powered display applications. The controller supports reliable operation of 0.3-WVGA, 0.24-VGA and 0.2-nHD DMDs. The DLPC2607 controller provides a convenient, multi-functional interface between system electronics and the DMD, enabling small form factor and low power displays.

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Technical documentation

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* Data sheet DLPC2607 Low-power DLP® Display Controller datasheet (Rev. E) PDF | HTML 01 Nov 2018

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