This reference design interfaces with Jacinto™ 7 processor EVM boards through the RGMII Ethernet Expansion Connector. Four automotive Ethernet connections are added through TI's automotive Ethernet physical layers (PHY). This design shows an implementation with TI's DP83TC818S-Q1 100Mbps and DP83TG721S-Q1 1000Mbps single-pair Ethernet (SPE) PHY. A coupling network is used to couple in 12V to the data line.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Detailed overview of design layout for component placement
Complete listing of design components, reference designators, and manufacturers/part numbers
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Detailed schematic diagram for design layout and components
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | 4 × Automotive Ethernet PHY Expansion for 100/1000Base-T1 Reference Design for Jacinto 7 Processors | PDF | HTML | Oct 13, 2024 |
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