CD4502B

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6 チャネル、3V ～ 18V インバータ

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データシート

document-pdfAcrobat CD4502B TYPES データシート (Rev. B) (英語)

CD4502B

アクティブ

データシート

ご注文はこちら

製品詳細

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

6

IOL (max) (mA)

14.4

IOH (max) (mA)

-2.4

Supply current (max) (µA)

120

Input type

Standard CMOS

Output type

Push-Pull

Features

Input clamp diode, Standard speed (tpd > 50ns)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Number of channels

6

IOL (max) (mA)

14.4

IOH (max) (mA)

-2.4

Supply current (max) (µA)

120

Input type

Standard CMOS

Output type

Push-Pull

Features

Input clamp diode, Standard speed (tpd > 50ns)

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

2 TTL-load output drive capability
3-state outputs
Common output-disable control
Inhibit control
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Noise Margin (full package-temperature range) =
   1 V at V_DD = 5 V
   2 V at V_DD = 10 V
   2.5 V at V_DD = 15 V
Applications:
- 3-state hex inverter for interfacing IC's with data buses
- COS/MOS to TTL hex buffer

2 TTL-load output drive capability
3-state outputs
Common output-disable control
Inhibit control
100% tested for quiescent current at 20 V
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"
Noise Margin (full package-temperature range) =
   1 V at V_DD = 5 V
   2 V at V_DD = 10 V
   2.5 V at V_DD = 15 V
Applications:
- 3-state hex inverter for interfacing IC's with data buses
- COS/MOS to TTL hex buffer

CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series I_OL standard.

The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series I_OL standard.

The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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