The ADS125R11, ADS125R13 and ADS125R14 are high
resolution, 24-bit, delta-sigma (ΔΣ), analog-to-digital converters with data rates up to
320kSPS with three, six and nine channels. The ADS125R11 and ADS125R14 are pin-to-pin
performance upgrades to the ADS1255 and ADS1256 ADCs.
The ADS125R1x devices provide low offset and
gain drift with low INL error. Autozero operation tracks offset error over time and
temperature. Three speed modes optimize power consumption, sample rate, bandwidth and
resolution for the application.
The ADCs are comprised of an input buffer, PGA, a
delta-sigma modulator and a low latency digital filter. The flexible input multiplexer
accepts single-ended and differential signals with integrated current sources for
open-sensor detection. The input buffer reduces measurement error caused by signal loading
of the sensor. The PGA provides gains up to x128 to increase measurement resolution.
The digital filter provides sample rates from
2.5SPS (for high resolution) to 320kSPS (for high throughput and high bandwidth
applications). In the 320kSPS mode, eight channels of data are measured in less than 300µs
with 16.9 bits effective resolution. The sinc3 filter provides greater than 100dB rejection
of 50Hz and 60Hz interference signals.
The SPI-compatible interface supports 2-, 3- or
4-wire communication modes. The SPI CRC helps to verify error-free transmission of data. The
register map CRC verifies register settings against unexpected changes. The general-purpose,
input-input digital pins offer an output signal for error detection, and a clock output to
synchronize other ADCs in multiple channel systems.
The ADS125R11, ADS125R13 and ADS125R14 are high
resolution, 24-bit, delta-sigma (ΔΣ), analog-to-digital converters with data rates up to
320kSPS with three, six and nine channels. The ADS125R11 and ADS125R14 are pin-to-pin
performance upgrades to the ADS1255 and ADS1256 ADCs.
The ADS125R1x devices provide low offset and
gain drift with low INL error. Autozero operation tracks offset error over time and
temperature. Three speed modes optimize power consumption, sample rate, bandwidth and
resolution for the application.
The ADCs are comprised of an input buffer, PGA, a
delta-sigma modulator and a low latency digital filter. The flexible input multiplexer
accepts single-ended and differential signals with integrated current sources for
open-sensor detection. The input buffer reduces measurement error caused by signal loading
of the sensor. The PGA provides gains up to x128 to increase measurement resolution.
The digital filter provides sample rates from
2.5SPS (for high resolution) to 320kSPS (for high throughput and high bandwidth
applications). In the 320kSPS mode, eight channels of data are measured in less than 300µs
with 16.9 bits effective resolution. The sinc3 filter provides greater than 100dB rejection
of 50Hz and 60Hz interference signals.
The SPI-compatible interface supports 2-, 3- or
4-wire communication modes. The SPI CRC helps to verify error-free transmission of data. The
register map CRC verifies register settings against unexpected changes. The general-purpose,
input-input digital pins offer an output signal for error detection, and a clock output to
synchronize other ADCs in multiple channel systems.