主页 逻辑和电压转换 电压转换器和电平转换器 电压转换器
主页
逻辑和电压转换
电压转换器和电平转换器
电压转换器

SN74LV161284

正在供货

19 位总线接口

立即订购
数据表

SN74LV161284

正在供货
数据表 立即订购

产品详情

Technology family LV-A Bits (#) 19 Data rate (max) (bps) 150000000 High input voltage (min) (V) 2 High input voltage (max) (V) 5.5 Vout (min) (V) 4.5 IOH (max) (A) -0.014 IOL (max) (A) 0.014 Supply current (max) (A) 0.07 Features Output enable, Partial power down (Ioff) Input type TTL-Compatible CMOS Output type 3-State, Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85 Applications IEEE1284 Rating Catalog
Technology family LV-A Bits (#) 19 Data rate (max) (bps) 150000000 High input voltage (min) (V) 2 High input voltage (max) (V) 5.5 Vout (min) (V) 4.5 IOH (max) (A) -0.014 IOL (max) (A) 0.014 Supply current (max) (A) 0.07 Features Output enable, Partial power down (Ioff) Input type TTL-Compatible CMOS Output type 3-State, Balanced CMOS, Push-Pull Operating temperature range (°C) -40 to 85 Applications IEEE1284 Rating Catalog
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • 4.5-V to 5.5-V VCC Operation
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JEDEC 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 300-V Machine Model (A115-A)
    • 2000-V Charged-Device Model (C101)
  • 4.5-V to 5.5-V VCC Operation
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 250 mA Per JEDEC 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 300-V Machine Model (A115-A)
    • 2000-V Charged-Device Model (C101)

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.

The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
filter 查找其他 电压转换器
下载 观看带字幕的视频 视频

您可能感兴趣的相似产品

open-in-new 比较替代产品
功能与比较器件相似
SN74LV8T245 正在供货 具有三态输出的单电源八路转换收发器 Wider voltage range

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 6
类型 标题 下载最新的英语版本 日期
* 数据表 SN74LV161284 数据表 (Rev. C) 2002年 11月 4日
应用手册 原理图检查清单 - 使用自动双向转换器进行设计的指南 PDF | HTML 英语版 PDF | HTML 2024年 12月 3日
应用手册 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
应用手册 了解 CMOS 输出缓冲器中的瞬态驱动强度与直流驱动强度 PDF | HTML 最新英语版本 (Rev.A) PDF | HTML 2024年 5月 15日
选择指南 Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
应用手册 Logic Solutions For IEEE Std 1284 1999年 6月 1日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

仿真模型

HSPICE Model for SN74LV161284

SCEM531.ZIP (111 KB) - HSpice Model
下载
仿真模型

SN74LV161284 IBIS Model (Rev. A)

SCEM021A.ZIP (96 KB) - IBIS Model
下载
封装 引脚 CAD 符号、封装和 3D 模型
SSOP (DL) 48 Ultra Librarian
TSSOP (DGG) 48 Ultra Librarian
应遵守 TI 评估类商品的标准条款与条件。

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

支持和培训

视频