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专用逻辑 IC

SN74AS286

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具有总线驱动器奇偶校验 I/O 端口的 9 位奇偶校验发生器/校验器

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SN74AS286

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产品详情

Technology family AS Bits (#) 9 Rating Catalog Operating temperature range (°C) 0 to 70
Technology family AS Bits (#) 9 Rating Catalog Operating temperature range (°C) 0 to 70
SOIC (D) 14 51.9 mm² 8.65 x 6
  • Generate Either Odd or Even Parity forNine Data Lines
  • Cascadable for n-Bit Parity
  • Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
  • Glitch-Free Bus During Power Up/Down
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 
  • Generate Either Odd or Even Parity forNine Data Lines
  • Cascadable for n-Bit Parity
  • Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
  • Glitch-Free Bus During Power Up/Down
  • Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.

The transmit () control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.

The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.

 

 

 

The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.

The transmit () control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.

The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.

 

 

 
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类型 标题 下载最新的英语版本 日期
* 数据表 9-Bit Parity Generators/Checker With Bus-Driver Parity I/O Port 数据表 (Rev. B) 1994年 12月 1日

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包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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