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LP2996A

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具有 DDR2/3/3L 关断引脚的 1.5A DDR 终端稳压器

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数据表

LP2996A

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产品详情

Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
Vin (min) (V) 1.35 Vin (max) (V) 5.5 Vout (min) (V) 0.656 Vout (max) (V) 0.698 Features Shutdown Pin for S3 Rating Catalog Operating temperature range (°C) 0 to 125 Iq (typ) (mA) 0.32 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L
HSOIC (DDA) 8 29.4 mm² 4.9 x 6
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown
  • Minimum VDDQ:
    • 1.8 V (LP2996-N)
    • 1.35 V (LP2996A)
  • Source and Sink Current
  • Low Output Voltage Offset
  • No External Resistors Required for Setting Output Voltage
  • Linear Topology
  • Suspend to Ram (STR) Functionality
  • Stable With Ceramic Capacitors With Appropriate ESR
  • Low External Component Count
  • Thermal Shutdown

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2996-N and LP2996A also incorporate a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.

An additional feature found on the LP2996-N and LP2996A is an active-low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but VREF remains active. A power savings advantage can be obtained in this mode through lower quiescent current.

TI recommends the LP2998 and LP2998-Q1 devices for automotive applications and DDR applications that require operating at temperatures below zero.

WEBENCH® design tools can be used by application designers to generate, optimize, and simlulate applications using the LP2998 and LP2998-Q1.
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类型 标题 下载最新的英语版本 日期
* 数据表 LP2996/LP2996A DDR Termination Regulator 数据表 (Rev. K) 2016年 12月 23日
应用手册 Limiting DDR Termination Regulators’ Inrush Current 2016年 8月 23日

设计和开发

如需其他信息或资源，请点击以下任一标题进入详情页面查看（如有）。

评估板

LP2998EVAL — 用于 LP2998 的评估板

The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.

用户指南: PDF
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仿真模型

LP2996A PSpice Transient Model

SNOM562.ZIP (85 KB) - PSpice Model
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仿真模型

LP2996A Unencrypted PSpice Transient Model

SNOM564.ZIP (7 KB) - PSpice Model
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参考设计

TIDA-010011 — 适用于保护继电器处理器模块的高效电源架构参考设计

该参考设计展示了各种电源架构，这些架构可为需要 >1A 负载电流和高效率的应用处理器模块生成多个电压轨。所需的电源通过来自背板的 5V、12V 或 24V 直流输入生成。电源通过带集成 FET 的直流/直流转换器生成并且使用带集成电感器的电源模块以减小尺寸。此设计采用 HotRod™ 封装类型，适用于需要低 EMI 的应用，也非常适合设计时间受限的应用。其他功能包括 DDR 端接稳压器、输入电源 OR-ing、电压时序控制、过载保护电子保险丝以及电压和负载电流监控。该设计可以用于处理器、数字信号处理器和现场可编程门阵列。该设计已依照 CISPR22 标准针对辐射发射进行了测试，符合 A (...)
原理图: PDF
参考设计

TIDEP0067 — 66AK2Gx DSP + ARM 处理器电源解决方案参考设计

此参考设计基于 66AK2Gx 多内核片上系统 (SoC) 处理器和配套 TPS65911 电源管理集成电路 (PMIC)，该电路在单个器件中包含适用于 66AK2Gx 处理器的电源和电源定序。该电源解决方案设计还包含支持 12V 输入的第一级降压转换器和用于 DDR3L 存储器的 DDR 终端稳压器。该参考设计经过了测试，包括硬件参考 (EVM)、软件（处理器 SDK）和测试数据。
设计指南: PDF
原理图: PDF
封装 引脚 CAD 符号、封装和 3D 模型
HSOIC (DDA) 8 Ultra Librarian
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订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点

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