74ACT16374

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具有三态输出的 16 位 D 类边沿触发触发器

产品详情

Number of channels 16 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 65 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family ACT Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock frequency (max) (MHz) 65 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 80 Features Balanced outputs, Positive input clamp diode, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
SSOP (DL) 48 164.358 mm² 15.88 x 10.35
  • Members of the Texas Instruments Widebus™ Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Bus-Driving True Outputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments Widebus™ Family
  • Inputs Are TTL-Voltage Compatible
  • 3-State Bus-Driving True Outputs
  • Flow-Through Architecture Optimizes PCB Layout
  • Distributed Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise
  • EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process
  • 500-mA Typical Latch-Up Immunity at 125°C
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

The SN54ACT16374 and 74ACT16374 are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

An output-enable input (OE) can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 74ACT16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit board area.

The SN54ACT16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16374 is characterized for operation from -40°C to 85°C.

The SN54ACT16374 and 74ACT16374 are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

An output-enable input (OE) can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state provides the capability to drive bus lines in a bus-organized system without need for interface or pullup components. OE does not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The 74ACT16374 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit board area.

The SN54ACT16374 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16374 is characterized for operation from -40°C to 85°C.

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SN74ACT374 正在供货 具有三态输出的八路 D 类边沿触发器 Voltage range (4.5V to 5.5V), average drive strength (24mA), average propagation delay (8ns)

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类型 标题 下载最新的英语版本 日期
* 数据表 16-Bit D-Type Edge-Triggered Flip-Flops With 3-State Outputs 数据表 (Rev. B) 1996年 4月 1日

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包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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