Home Interface LVDS, M-LVDS & PECL ICs
Home
Interface
LVDS, M-LVDS & PECL ICs

SN65ELT23

ACTIVE

5-V dual differential PECL buffer to TTL translator

Order now
Data sheet

SN65ELT23

ACTIVE
Data sheet Order now

Product details

Function Receiver, Translator Protocols PECL Number of transmitters 0 Number of receivers 2 Signaling rate (Mbps) 500 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
Function Receiver, Translator Protocols PECL Number of transmitters 0 Number of receivers 2 Signaling rate (Mbps) 500 Input signal PECL Output signal TTL Rating Catalog Operating temperature range (°C) -40 to 85
VSSOP (DGK) 8 14.7 mm² (3 mm × 4.9 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm)
  • Dual 5-V Differential PECL-to-TTL Buffer
  • 24-mA TTL Ouputs
  • Operating Range
    • PECL VCC = 4.75 V to 5.25 V with GND = 0 V
  • Support for Clock Frequencies of 250 MHz (TYP)
  • 3.5-ns Typical Propagation Delay
  • Output Default Low with Inputs Left Open or <1.3 V
  • Internal Input 50-k Pull-Down Resistor
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC100ELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data
  • Dual 5-V Differential PECL-to-TTL Buffer
  • 24-mA TTL Ouputs
  • Operating Range
    • PECL VCC = 4.75 V to 5.25 V with GND = 0 V
  • Support for Clock Frequencies of 250 MHz (TYP)
  • 3.5-ns Typical Propagation Delay
  • Output Default Low with Inputs Left Open or <1.3 V
  • Internal Input 50-k Pull-Down Resistor
  • Built-In Temperature Compensation
  • Drop-In Compatible to the MC100ELT23
  • APPLICATIONS
    • Data and Clock Transmission Over Backplane
    • Signaling Level Conversion for Clock or Data

The SN65ELT23 is a low power dual PECL-to-TTL translator device. The device includes circuitry to maintain a known logic low level when inputs are in an open condition. The SN65ELT23 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.

The SN65ELT23 is a low power dual PECL-to-TTL translator device. The device includes circuitry to maintain a known logic low level when inputs are in an open condition. The SN65ELT23 is housed in an industry standard SOIC-8 package and is also available in an optional TSSOP-8 package.
filter Find other LVDS, M-LVDS & PECL ICs
Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Similar functionality to the compared device.
SN65ELT22 ACTIVE 5-V dual TTL to differential PECL translator Driver variant

Technical documentation

No results found. Please clear your search and try again.
View all 2
Top documentation Type Title Format options Date
* Data sheet 5-V Dual Differential PECL Buffer-to-TTL Translator datasheet Jun 30, 2009
Application note AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) Oct 17, 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Package Pins CAD symbols, footprints & 3D models
VSSOP (DGK) 8 Ultra Librarian
SOIC (D) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos