Home Data converters Analog-to-digital converters (ADCs) High-speed ADCs (≥10 MSPS)
Home
Data converters
Analog-to-digital converters (ADCs)
High-speed ADCs (≥10 MSPS)

ADC12QJ1600-SEP

ACTIVE

Radiation-tolerant, 30-krad, 12-bit, quad 1.6-GSPS ADC with JESD204C interface

Order now
Data sheet

ADC12QJ1600-SEP

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (Bits) 9 SFDR (dB) 64 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
Sample rate (max) (Msps) 1600 Resolution (Bits) 12 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1910 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (Bits) 9 SFDR (dB) 64 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 30 Radiation, SEL (MeV·cm2/mg) 43
FCCSP (ALR) 144 100 mm² 10 x 10
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 outgassing specification
    • Vendor item drawing (VID) V62/22610
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20 BFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2 – 8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V
  • Radiation Tolerance:
    • Total Ionizing Dose (TID): 30krad (Si)
    • Single Event Latchup (SEL): 43 MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Space-enhanced plastic (space EP):
    • Meets ASTM E595 outgassing specification
    • Vendor item drawing (VID) V62/22610
    • Temperature range: –55°C to 125°C
    • One fabrication, assembly, and test site
    • Wafer lot traceability
    • Extended product life cycle
    • Extended product change notification
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100 MHz): 57.4dBFS
    • ENOB (100 MHz): 9.1 Bits
    • SFDR (100 MHz): 64dBc
    • Noise floor (–20 BFS): –147dBFS
  • Full-scale input voltage: 800mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2 – 8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS): 1.9W
  • Power supplies: 1.1V, 1.9V

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the device suited for a variety of mulch-chanel communications systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.
filter Find other High-speed ADCs (≥10 MSPS)
Download View video with transcript Video

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet ADC12QJ1600-SEP Quad Channel 1.6-GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 24 Feb 2025
* Radiation & reliability report ADC12QJ1600-SEP Production Flow and Reliability Report (Rev. A) PDF | HTML 12 Mar 2025

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC12QJ1600EVM — ADC12QJ1600 evaluation module for quad-channel, 12-bit, 1.6GSPS ADC with JESD204C interface

The ADC12QJ1600 evaluation module (EVM) is designed to evaluate the ADC12QJ1600-Q1 family of high-speed analog-to-digital converters (ADCs). The EVM is populated with the ADC12QJ1600-Q1, a 12-bit, quad-channel 1.6GSPS ADC with JESD204B interface and allows for evaluation of all sample rates and (...)
User guide: PDF
Not available on TI.com
Simulation model

ADC09xJ800, ADC09xJ1300, ADC12xJ800 and ADC12xJ1600 IBIS-AMI Model (Rev. A)

SBAM512A.ZIP (22293 KB) - IBIS-AMI Model
Download
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Request
Package Pins CAD symbols, footprints & 3D models
FCCSP (ALR) 144 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos