RGMII is a high-bandwidth data bus protocol with very strict timing considerations. The following device recommendations are provided as a suggested solution as they can support the data rates required for RGMII interfaces; however, because the RGMII specification is defined without consideration for voltage level translation, board-level assessment of key timing parameters and assessment of performance within the system is encouraged.

• Board layout is critical to the success of RGMII translation; we recommend using signal integrity simulations and prototyping for any design
• Use active translators for maximum data rate
• Use one device for all TX signals and one for all RX signals to minimize channel-to-channel skew
• See Low Voltage Translation For SPI, UART, RGMII, JTAG Interfaces for details regarding the performance of SN74AXC8T245 in RGMII applications
• Place translators closest to the low-voltage device, if possible, to improve signal integrity
• Consider source-terminating signals if sent over 12 cm (4700 mil) or longer traces
• Need additional assistance? Ask our engineers a question on the TI E2E™ logic support forum