The TSW12QJ1600 evaluation module (EVM) is designed to evaluate the ADC12QJ1600-Q1 family of high-speed analog-to-digital converters (ADCs) with different front-end options. The EVM is populated with dual ADC12QJ1600-Q1, a 12-bit, quad-channel 1.6GSPS ADC with JESD204B interface and allows for evaluation of multiple ADC synchronizations, deterministic latency, and test the performance of the ADC with various front-end options (AC-coupled transformer; DC-coupled option with LMH32401). The design also demonstrates how the clocking scheme can be simplified by daisy-chaining the PLL reference output (PLLREFO+, PLLREFO-) from one ADC to another, eliminating the need for the clock-distribution chip that is usually needed by JESD devices.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | EVM User's guide | TSW12QJ1600 Evaluation Module User's Guide | 20 Jul 2020 | |
| Certificate | TSW12QJ1600EVM EU Declaration of Conformity (DoC) | 29 Jul 2020 |
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