TIDA-00467

Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design

TIDA-00467

Design files

Overview

A common technique to estimate the position of emitters uses the amplitude and phase shift data of a signal derived from an array of spatially distributed sensors. For such systems, it is important to guarantee a deterministic phase relationship between the sensors to minimize errors in the actual measured data. This application design will discuss how multiple Analog to Digital Converters (ADCs) with a JESD204B interface can be synchronized so that the
sampled data from the ADCs are phase aligned.

Features
  • Synchronized 2 giga sample ADCs sampling at 3.072GHz
  • System expandable to more than 2 ADCs
  • Phase variation less than 1 ADC clock period
  • Easy to use software interface for control and data acquisition
  • Excellent spur and noise perfromance of ADC at 3.072GHz
  • This design is tested and includes software, demo hardware and a design guide.
Industrial
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

TIDU851.PDF (604 KB)

Reference design overview and verified performance test data

TIDRE87.PDF (1262 KB)

Detailed overview of design layout for component placement

TIDRE88.PDF (117 KB)

Detailed overview of design layout for component placement

TIDRE85.PDF (318 KB)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRE86.PDF (216 KB)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRE90.ZIP (9933 KB)

Files used for 3D models or 2D drawings of IC components

TIDCA48.ZIP (712 KB)

Design file that contains information on physical board layer of design PCB

TIDCA49.ZIP (1437 KB)

Design file that contains information on physical board layer of design PCB

TIDRE89.PDF (2955 KB)

PCB layer plot file used for generating PCB design layout

TIDRE83.PDF (1278 KB)

Detailed schematic diagram for design layout and components

TIDRE84.PDF (251 KB)

Detailed schematic diagram for design layout and components

Products

Includes TI products in the design and potential alternatives.

Clock jitter cleaners

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12J400012-Bit, 4.0-GSPS, RF Sampling Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML

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Software

Support software

TIDCA50 — TIDA-00467 Software

Supported products & hardware

Supported products & hardware

Hardware development
Reference design
TIDA-00467 Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design
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TIDCA50 TIDA-00467 Software

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Latest version
Version: 01.00.00.00
Release date: Apr 12, 2015
Hardware development
Reference design
TIDA-00467 Synchronizing Multiple JESD204B ADCs for Emitter Position Location Reference Design

Release Information

The design resource accessed as www.ti.com/lit/zip/tidca50 or www.ti.com/lit/xx/tidca50/tidca50.zip has been migrated to a new user experience at www.ti.com/tool/download/TIDCA50. Please update any bookmarks accordingly.

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* Design guide Synchronizing Multiple JESD204B ADCs for Emitter Position Location Design Guide Mar 24, 2015

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