This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications. The tradeoffs considered include balun construction, insertion loss, dynamic performance, configurability, and ease of implementation. Topology and layout play a critical role in optimizing system performance, which is why these designs can help to reduce designs cycles.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed schematic diagram for design layout and components
Detailed schematic diagram for design layout and components
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Driving GSPS ADCs in Single- or Dual-Channel Mode Design Guide (Rev. A) | Jul 1, 2015 |
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