SLASFB7A
November 2024 – August 2025
TAS5802
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
Device Comparison Table
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Timing Requirements
5.7
Typical Characteristics
5.7.1
Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
5.7.2
Bridge Tied Load (BTL) Configuration Curves with BD Modulation
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Power Supplies
6.3.2
Device Clocking
6.3.3
Serial Audio Port – Clock Rates
6.3.4
Serial Audio Port (SAP)
6.3.5
Digital Audio Processing
6.3.6
Class D Audio Amplifier
6.3.6.1
Speaker Amplifier Gain Select
6.4
Device Functional Modes
6.4.1
Software Control
6.4.2
Speaker Amplifier Operating Modes
6.4.2.1
BTL Mode
6.4.3
Low EMI Modes
6.4.3.1
Spread Spectrum
6.4.3.2
Channel to Channel Phase Shift
6.4.3.3
Multi-Devices PWM Phase Synchronization
6.4.4
Thermal Foldback
6.4.5
Device State Control
6.4.6
Device Modulation
6.4.6.1
BD Modulation
6.4.6.2
1SPW Modulation
6.4.6.3
Hybrid Modulation
6.5
Programming and Control
6.5.1
I2C Serial Communication Bus
6.5.2
Target Address
6.5.2.1
Random Write
6.5.2.2
Sequential Write
6.5.2.3
Random Read
6.5.2.4
Sequential Read
6.5.2.5
DSP Memory Book, Page and BQ update
6.5.2.6
Checksum
6.5.2.6.1
Cyclic Redundancy Check (CRC) Checksum
6.5.2.6.2
Exclusive or (XOR) Checksum
6.5.3
Control via Software
6.5.3.1
Startup Procedures
6.5.3.2
Shutdown Procedures
6.5.3.3
Protection and Monitoring
6.5.3.3.1
Overcurrent Shutdown (OCSD)
6.5.3.3.2
DC Detect
6.5.3.3.3
Device Over Temperature Protection
6.5.3.3.4
Over Voltage Protection
6.5.3.3.5
Under Voltage Protection
6.5.3.3.6
Clock Fault
7
Register Maps
7.1
CONTROL PORT Registers
8
Application and Implementation
8.1
Application Information
8.1.1
Bootstrap Capacitors
8.1.2
Inductor Selections
8.1.3
Power Supply Decoupling
8.1.4
Output EMI Filtering
8.2
Typical Applications
8.2.1
2.0 (Stereo BTL) System
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedures
8.2.1.2.1
Step 1: Hardware Integration
8.2.1.2.2
Step 2: Speaker Tuning
8.2.1.2.3
Step 3: Software Integration
8.3
Power Supply Recommendations
8.3.1
DVDD Supply
8.3.2
PVDD Supply
8.4
Layout
8.4.1
Layout Guidelines
8.4.1.1
General Guidelines for Audio Amplifiers
8.4.1.2
Importance of PVDD Bypass Capacitor Placement on PVDD Network
8.4.1.3
Optimizing Thermal Performance
8.4.1.3.1
Device, Copper, and Component Layout
8.4.1.3.2
Stencil Pattern
8.4.1.3.2.1
PCB footprint and Via Arrangement
8.4.1.3.2.2
Solder Stencil
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Device Support
9.1.1
Device Nomenclature
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
PACKAGE OPTION ADDENDUM
11.1
Tape and Reel Information
11.2
Mechanical Data
Package Options
Mechanical Data (Package|Pins)
PWP|28
MPDS373B
Thermal pad, mechanical data (Package|Pins)
PWP|28
PPTD351
Orderable Information
slasfb7a_oa
slasfb7a_pm
Data Sheet
TAS5802
22W Stereo, Inductor-Less, Digital Input, Closed-Loop Class-D Audio Amplifier with 96Khz Extended Processing and Low Idle Power Dissipation