SNAS944 August   2025 LMK3H2104

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 LP-HCSL Test or Simulation Loads
    2. 6.2 LVDS Test Load
    3. 6.3 LVCMOS Test Load
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GPI/GPIO
        1. 7.3.1.1 GPI/GPIO Pin Functions
        2. 7.3.1.2 GPI/GPIO Configurations
        3. 7.3.1.3 I2C Address Through GPI/GPIO
        4. 7.3.1.4 GPIO Pins In 3-Level Input Mode
        5. 7.3.1.5 GPI/GPIO Internal Pullup And Pulldown
      2. 7.3.2  OTP
        1. 7.3.2.1 OTP Overview
        2. 7.3.2.2 OTP Page Selection
        3. 7.3.2.3 OTP Page Selection Timing
        4. 7.3.2.4 Output Behaviors During Dynamic OTP Page Change
      3. 7.3.3  PWRGD/PWRDN#
        1. 7.3.3.1 PWRGD/PWRDN# Function Assignment
        2. 7.3.3.2 PWRGD
        3. 7.3.3.3 PWRDN#
      4. 7.3.4  Power Supply
        1. 7.3.4.1 Power Supply Pin Mapping
        2. 7.3.4.2 Unused Power Supply Pins
      5. 7.3.5  Power Up Sequence
        1. 7.3.5.1 Power Up Sequence
      6. 7.3.6  Output Enable And Disable
        1. 7.3.6.1 OE Registers
        2. 7.3.6.2 OE Group Assignment
        3. 7.3.6.3 OE AND Logic
        4. 7.3.6.4 Alternative OE
        5. 7.3.6.5 OE Polarity
        6. 7.3.6.6 Single LVCMOS OE
        7. 7.3.6.7 LOS And Output Behaviors
      7. 7.3.7  PERST#
        1. 7.3.7.1 PERST# Buffer Mode
        2. 7.3.7.2 PERST# Latching
      8. 7.3.8  Status Signals
        1. 7.3.8.1 CLK_READY
        2. 7.3.8.2 Input LOS
        3. 7.3.8.3 Output Frequency Detection
        4. 7.3.8.4 CRC_ERROR
        5. 7.3.8.5 Status Event Registers
        6. 7.3.8.6 Device Interrupt
        7. 7.3.8.7 Status Signals From GPIO
      9. 7.3.9  Input Receiver
        1. 7.3.9.1 GPI Input And Clock Input
        2. 7.3.9.2 Clock Input Configuration And Termination
        3. 7.3.9.3 Differential Clock Inputs
        4. 7.3.9.4 Fail-Safe Input
      10. 7.3.10 Input Switching
        1. 7.3.10.1 Automatic Switching
        2. 7.3.10.2 Manual Switching
      11. 7.3.11 Output MUX
        1. 7.3.11.1 Clock Output MUX Settings
      12. 7.3.12 Output Driver
        1. 7.3.12.1  Output Formats
        2. 7.3.12.2  1.2V LVCMOS Output
        3. 7.3.12.3  LVCMOS Output Impedance
        4. 7.3.12.4  Programmable Slew Rate
        5. 7.3.12.5  Output Polarities
        6. 7.3.12.6  Double Terminated LP-HCSL Outputs
        7. 7.3.12.7  AC- And DC-LVDS
        8. 7.3.12.8  LVDS Output Common Mode
        9. 7.3.12.9  Output Disable States
        10. 7.3.12.10 Output Behaviors During Change of State
      13. 7.3.13 Output Synchronization
        1. 7.3.13.1 Output Synchronization
        2. 7.3.13.2 Synchronous And Asynchronous OE
      14. 7.3.14 Output Phase Shift
      15. 7.3.15 Dynamic Frequency Change
        1. 7.3.15.1 FOD Configuration Update
        2. 7.3.15.2 Channel Divider Update
        3. 7.3.15.3 DCO Mode
    4. 7.4 SSC
    5. 7.5 Device Functional Modes
      1. 7.5.1 Fractional Output Divider
        1. 7.5.1.1 FOD Operation
        2. 7.5.1.2 Edge Combiner
        3. 7.5.1.3 Integer Boundary Spurs
      2. 7.5.2 Buffer Only Mode
    6. 7.6 Programming
      1. 7.6.1 I2C Serial Interface
      2. 7.6.2 Vendor ID
      3. 7.6.3 OTP Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application Block Diagram Example
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Data Sheet

LMK3H2104 4-Output PCIe Gen 1-7 Compliant Low jitter General Purpose BAW Clock Generator