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  • Enhancing Server Power Design Using Advanced Features of TI’s Smart eFuses

    • SLVAFR8 January   2025 TPS1685 , TPS1689 , TPS25984 , TPS25984B , TPS25985 , TPS25990

       

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  • Enhancing Server Power Design Using Advanced Features of TI’s Smart eFuses
  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Over-Current Response of Conventional eFuse Devices
  6. 3Challenges with Current Limit Functionality
  7. 4Proposed Design Using TI's High-Current eFuses
    1. 4.1 Steady-State Over-Current Protection in TPS25984, TPS25985, TPS25990, and TPS1685 eFuses
    2. 4.2 Design Guideline
  8. 5Thermal Performance with Continual Transient Load Current
  9. 6System Level Advantages with TI's eFuse Design
    1. 6.1 Lower Number of eFuses to be Connected in Parallel
    2. 6.2 Reduced PSU Size
  10. 7Summary
  11. 8References
  12. IMPORTANT NOTICE
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Application Note

Enhancing Server Power Design Using Advanced Features of TI’s Smart eFuses

Abstract

This application note explains and demonstrates two different over-current protection mechanisms that the different eFuse devices provide. One is called current-limit, and another is circuit-breaker. Using experimental results, this article also discusses the limitations of the current-limit-based over-current protection in enterprise server applications, where the power delivery system is exposed to high slew-rate, high frequency, and high amplitude load transients. The limitations of the approach as mentioned above are solved through the circuit-breaker mechanism along with a programmable over-current blanking timer in TI’s high-current eFuse family of devices. This design is discussed in this application note through experimental results. The system-level benefits of using TI’s high-current eFuse design over the conventional eFuse devices available in the market are also discussed.

Trademarks

Intel® is a registered trademark of Intel Corporation.

All trademarks are the property of their respective owners.

1 Introduction

A typical power tree of an enterprise server motherboard is shown in Figure 1-1. With the advancement of artificial intelligence and machine learning, graphics processing units (GPUs) are becoming more and more power-hungry over time and demand high slew-rate and amplitude current pulses to improve the processor computation speed. Figure 1-2 depicts a typical load transient profile seen at the 12V bus (50A to 110A load transient) while applying a load transient of 300A for 8ms to 675A for 2ms and then 300A for 8ms (as per Intel® Birch Stream server platform) at the output of VRM with 1.8V. To support these load transients at the output of the voltage regulator modules (VRMs), the power stages of the VRMs have to draw the pulse currents from the input power supply unit (PSU) as the input and output filters of the VRMs are unable to support these high-frequency load transients. As shown in Figure 1-1, the input power path protection devices, eFuses are placed in between the PSU and the power stages of VRMs for inrush current management and protecting the PSUs and the VRMs against different faults, such as input under-voltage, input over-voltage, power up into output short, over-current, output hot-short, etc. The over-current protection mechanism needs to be implemented inside the eFuses so that these devices can protect the system against a persistent over-current fault whereas the transient peak current pulses of a certain amplitude and duration must be allowed to pass through.

 Enterprise Server Power Block
                Diagram Figure 1-1 Enterprise Server Power Block Diagram
 A Typical Load Transient Profile
                Seen at the 12V Bus Powering a VRM with 1.8V Output Figure 1-2 A Typical Load Transient Profile Seen at the 12V Bus Powering a VRM with 1.8V Output

 

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