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  • Scanning Comparator

    • SLAAEO6A September   2024  – August 2025 MSPM0C1106 , MSPM0G3507

       

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  • Scanning Comparator
  1.   1
  2. 1 Description
  3. 2 Required Peripherals
  4. 3 Design Steps
  5. 4 Design Considerations
  6. 5 Software Flow Chart
  7. 6 Application Code
  8. 7 Results
  9. 8 Additional Resources
  10. 9 E2E
  11. 10Revision History
  12.   Trademarks
  13. IMPORTANT NOTICE
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Subsystem Design

Scanning Comparator

1 Description

This subsystem demonstrates how to represent multiple comparators with a single integrated comparator and software in an MSPM0 microcontroller. The process allows the designer to maximize the comparator function and utilize more theoretical comparators than are physically on the device. This example specifically cycles through three different comparator configurations and input pins while setting three output pins with the results as shown in Figure 1-1.

MSPM0G3507, MSPM0L1306 Theoretical Function of
                    Scanning Comparator Subsystem Figure 1-1 Theoretical Function of Scanning Comparator Subsystem

Utilizing the customizable IO MUXing for the MSPM0 comparator, this example enables multiple signal inputs for the same comparator. The three signal inputs for this example are on the COMP_IN0+, COMP_IN0-, and COMP_IN1- pins as shown in Figure 1-2.

MSPM0G3507, MSPM0L1306 Comparator Input and Output
                    MUXes Figure 1-2 Comparator Input and Output MUXes

2 Required Peripherals

Table 2-1 describes the required integrated COMP and GPIOs.

Table 2-1 Required Peripherals
Peripheral Used Notes
Comparator Called COMP_INST in code (Includes 8-bit reference DAC)
GPIO The three GPIOs are referred to as pins A, B, and C.

 

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