SLAAEG4B October 2023 – July 2025 MSPM0C1104 , MSPM0C1106 , MSPM0L1306
The MSPM0 C-series microcontroller (MCU) portfolio offers a wide variety of low cost 32-bit MCUs with ultra-low-power and integrated analog and digital peripherals for sensing, measurement and control applications. This application note covers information needed for hardware development with MSPM0 C-series MCUs, including detailed hardware design information for power supplies, reset circuitry, clocks, debugger connections, key analog peripherals, communication interfaces, GPIOs, and board layout guidance.
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Table 1-1 describes the main signal that needs to be checked during the MSPM0C hardware design process. The following sections provide more details.
Pin (1) | Description | Requirements |
---|---|---|
VDD | Power supply positive pin | Place 10µF and 100nF capacitors between VDD and VSS, and keep those part close to VDD and VSS. |
VSS | Power supply negative pin | |
NRST | Reset pin | Connect an external 47kΩ pullup resistor with a 10nF pulldown capacitor. |
VREF+(2) | Voltage reference power supply for external reference input | When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source. Keep open is OK if external voltage reference is not used. |
VREF-(2) | Voltage reference ground supply for external reference input | |
SWCLK | Serial wire clock from debug probe | Internal pulldown to VSS, does not need any external part. |
SWDIO | Bidirectional (shared) serial wire data | Internal pullup to VDD, does not need any external part. |
PA0, PA1 | Open-drain I/O | Pull-up resistor required for output high |
PA18(2) | Default BSL invoke pin | Keep pulled down to avoid entering BSL mode after reset. (BSL invoke pin can be remapped.) |
PAx (exclude PA0, PA1) | General-purpose I/O | Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. |
TI recommends connecting a combination of a 10μF and a 0.1nF low-ESR ceramic decoupling capacitor to the VDD and VSS pins. Higher-value capacitors can be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the decoupled pins (within a few millimeters).
The NRST reset pin is required to connect an external 47kΩ pullup resistor with a 10nF pulldown capacitor.
For MSPM0C1105 and MSPM0C1106 which support external crystals, external bypass capacitors for the crystal oscillator pins are required when using external crystals.
For 5V-tolerant open drain (ODIO), a pullup resistor is required to output high, this is required for inter-integrated circuit (I2C) and universal asynchronous receiver/transmitter (UART) functions if the ODIO are used.