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  • PCM6xx0-Q1 Power Consumption Matrix Across Various Usage Scenario

    • SBAA500A May   2021  – September 2021 PCM6020-Q1 , PCM6240-Q1 , PCM6260-Q1 , PCM6340-Q1

       

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  • PCM6xx0-Q1 Power Consumption Matrix Across Various Usage Scenario
  1.   Trademarks
  2. 1Introduction
  3. 2Slave Mode Power Consumption with PLL Enabled
  4. 3Slave Mode Power Consumption with PLL Disabled
  5. 4Digital Microphone Power Consumption
  6. 5MICBIAS Power Consumption
  7. 6Settings for Lowest Power Consumption
  8. 7Revision History
  9. IMPORTANT NOTICE
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APPLICATION NOTE

PCM6xx0-Q1 Power Consumption Matrix Across Various Usage Scenario

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

Power consumption on PCM6xx0 devices is highly dependent on the usage scenario and features enabled on these devices. The following tables summarize the power consumption based on the following:

  • Supply voltage
  • Sampling Frequency (FS)
  • Number of channels
  • Decimation filter options
  • Bit clock (BCLK) to Frame sync (FSYNC) ratio
  • PLL enabled or disabled
  • Converted word length

The tables report the average active current consumed on the Analog Supply, AVDD. This supply includes all the internal analog and digital circuits, but excludes the current consumed by the I/O pins due to its application dependencies. I/O power is dependent upon the following:

  • Load capacitance of the system bus interface
  • Data output clock rate
  • Data conversion output activity
  • Bus interface pullups or pull downs
  • Frequency of ADC commands sent by microprocessor

2 Slave Mode Power Consumption with PLL Enabled

Table 2-1 describes the typical current consumption of the PCM6xx0 when the PLL is enabled with AVDD set to 3.3 V. The PLL is enabled by:

  • Setting the bitfield PLL_PDZ in the PWR_CFG register
  • Applying a FSYNC and BCLK with the desired sampling rate and BCLK to FSYNC ratio

The current consumption measurements had the AGC and the Biquad Filters disabled.

Table 2-1 Typical Current Consumption (PLL Enabled)
SAMPLING FREQUENCY (kHz) ADC CHANNELS DECIMATION FILTERS BCLK RATIO WORD LENGTH AVDD CURRENT AT 3.3 V (mA)
8 1 Linear Phase 32 32 10.65
Low Latency 8.56
2 Linear Phase 48 24 14.40
Low Latency 13.72
3 Linear Phase 96 16.88
Low Latency 18.04
4 Linear Phase 22.09
Low Latency 21.98
5 Linear Phase 144 25.79
Low Latency 27.70
6 Linear Phase 31.14
Low Latency 30.84
16 1 Linear Phase 24 24 10.59
Low Latency 9.65
2 Linear Phase 48 12.85
Low Latency 13.27
3 Linear Phase 96 19.09
Low Latency 17.37
4 Linear Phase 24.03
Low Latency 23.92
5 Linear Phase 144 28.69
Low Latency 27.88
6 Linear Phase 30.93
Low Latency 31.40
24 1 Linear Phase 24 24 9.14
Low Latency 8.89
2 Linear Phase 48 14.38
Low Latency 14.39
3 Linear Phase 96 19.43
Low Latency 18.09
4 Linear Phase 21.81
Low Latency 22.50
5 Linear Phase 144 28.65
Low Latency 27.32
6 Linear Phase 32.91
32 1 Linear Phase 24 24 10.56
Low Latency 10.24
2 Linear Phase 48 13.17
Low Latency 14.42
3 Linear Phase 96 17.66
Low Latency 19.77
4 Linear Phase 22.82
Low Latency 22.32
5 Linear Phase 144 29.09
Low Latency 27.23
6 Linear Phase 33.62
Low Latency 31.98
48 1 Linear Phase 24 24 10.07
Low Latency 11.01
2 Linear Phase 48 14.92
Low Latency 15.15
3 Linear Phase 96 18.69
Low Latency 19.58
4 Linear Phase 24.22
Low Latency 25.25
5 Linear Phase 144 28.49
Low Latency 28.65
6 Linear Phase 34.32
Low Latency 33.56
44.1 1 Linear Phase 24 24 8.72
2 Linear Phase 48 15.17
3 Linear Phase 96 20.04
4 Linear Phase 25.28
5 Linear Phase 144 28.05
6 Linear Phase 34.10
96 1 Linear Phase 24 24 12.00
Low Latency 12.45
2 Linear Phase 48 16.58
Low Latency 17.39
3 Linear Phase 96 22.11
Low Latency 21.35
4 Linear Phase 29.42
Low Latency 26.91
192 1 Linear Phase 24 24 11.29
Low Latency 13.14
2 Linear Phase 48 16.00
Low Latency 18.28
3 Linear Phase 96 22.94
Low Latency 25.05
4 Linear Phase 27.43
Low Latency 29.60
384 1 Linear Phase 24 24 13.67
Low Latency 13.96
2 Linear Phase 48 20.33
Low Latency 20.47

3 Slave Mode Power Consumption with PLL Disabled

Table 3-1 describes the typical current consumption of the PCM6xx0 when the PLL is disabled with AVDD set to 3.3 V. The PLL is disabled by:

  • Clearing the bitfield PLL_PDZ in the PWR_CFG register
  • Applying a master clock through BCLK, GPIO1, or the GPIx pins
  • If GPIO1 is configured as MCLK, setting the appropriate GPIO1_CFG bitfield in the GPIO_CFG0 register
  • Indicating the master clock source through DIS_PLL_SLV_CLK_SRC bitfield in the CLK_SRC register
  • Setting the appropriate MCLK to FSYNC ratio through the MCLK_RATIO_SEL bitfield and MCLK_FREQ_SEL_MODE bitfield of the CLK_SRC register
  • Setting the AUTO_MODE_PLL_DIS bitfield and the corresponding MCLK_FREQ_SEL bitfield of the MST_CFG0 register

The current consumption measurements had the AGC and the Biquad Filters disabled.

Table 3-1 Typical Current Consumption (PLL Disabled)
SAMPLING FREQUENCY (kHz) MCLK FREQUENCY(MHz) MCLK RATIO ADC CHANNELS DECIMATION FILTERS BCLK RATIO WORD LENGTH AVDD CURRENT AT 3.3V (mA)
8 12.288 1536 1 Linear Phase 32 32 7.15
2 48 24 11.45
3 96 14.95
4 20.76
5 144 23.56
6 144 27.95
16 12.288 768 1 Linear Phase 24 24 8.18
Low Latency 8.21
Ultra-Low Latency 8.73
2 Linear Phase 48 11.98
Low Latency 12.64
Ultra-Low Latency 10.71
3 Linear Phase 96 16.64
Low Latency 17.06
Ultra-Low Latency 16.77
4 Linear Phase 19.06
Low Latency 20.99
Ultra-Low Latency 18.96
5 Linear Phase 144 23.25
Low Latency 23.71
Ultra-Low Latency 22.71
6 Linear Phase 28.62
Low Latency 28.57
Ultra-Low Latency 27.32
16 24.576 1536 1 Linear Phase 24 24 8.53
Low Latency 7.91
Ultra-Low Latency 8.08
2 Linear Phase 48 12.74
Low Latency 13.34
Ultra-Low Latency 13.35
3 Linear Phase 96 16.02
Low Latency 16.15
Ultra-Low Latency 17.17
4 Linear Phase 21.53
Low Latency 21.98
Ultra-Low Latency 19.91
5 Linear Phase 144 25.77
Low Latency 26.18
Ultra-Low Latency 24.08
6 Linear Phase 192 32 30.32
Low Latency 30.67
Ultra-Low Latency 28.59
16 36.864 2304 1 Linear Phase 24 24 7.78
Low Latency 9.43
Ultra-Low Latency 7.56
2 Linear Phase 48 12.70
Low Latency 11.86
Ultra-Low Latency 12.54
3 Linear Phase 96 16.47
Low Latency 18.33
Ultra-Low Latency 16.02
4 Linear Phase 21.77
Low Latency 21.18
Ultra-Low Latency 22.35
5 Linear Phase 144 25.70
Low Latency 25.45
Ultra-Low Latency 26.54
6 Linear Phase 30.67
Low Latency 31.44
Ultra-Low Latency 29.69
24 12.288 512 1 Linear Phase 24 24 8.44
Low Latency 7.03
Ultra-Low Latency 6.61
2 Linear Phase 48 13.08
Low Latency 12.48
Ultra-Low Latency 64 32 11.14
3 Linear Phase 96 24 16.59
Low Latency 15.20
Ultra-Low Latency 17.17
4 Linear Phase 18.89
Low Latency 20.84
Ultra-Low Latency 20.50
5 Linear Phase 144 23.01
Low Latency 24.74
Ultra-Low Latency 24.75
6 Linear Phase 192 32 27.52
Low Latency 28.47
Ultra-Low Latency 27.9
24.576 1024 1 Linear Phase 32 32 8.03
Low Latency 7.74
Ultra-Low Latency 8.33
2 Linear Phase 64 13.53
Low Latency 11.87
Ultra-Low Latency 13.55
3 Linear Phase 128 17.23
Low Latency 18.33
Ultra-Low Latency 15.93
4 Linear Phase 21.82
Low Latency 20.81
Ultra-Low Latency 21.46
5 Linear Phase 192 24.61
Low Latency 25.04
Ultra-Low Latency 26.59
6 Linear Phase 29.65
Low Latency 30.13
Ultra-Low Latency 28.37
24 36.864 1536 1 Linear Phase 24 24 8.58
Low Latency 9.84
Ultra-Low Latency 8.08
2 Linear Phase 48 14.00
Low Latency 13.77
Ultra-Low Latency 13.00
3 Linear Phase 96 17.42
Low Latency 17.37
Ultra-Low Latency 18.34
4 Linear Phase 22.98
Low Latency 22.62
Ultra-Low Latency 23.00
5 Linear Phase 144 27.30
Low Latency 26.04
Ultra-Low Latency 27.16
6 Linear Phase 192 32 31.47
Low Latency 31.44
Ultra-Low Latency 29.87
32 12.288 384 1 Linear Phase 24 24 7.01
Low Latency 6.87
Ultra-Low Latency 8.91
2 Linear Phase 48 12.72
Low Latency 11.84
Ultra-Low Latency 64 32 12.27
3 Linear Phase 96 24 17.2
Low Latency 15.68
Ultra-Low Latency 14.93
4 Linear Phase 18.81
Low Latency 18.74
Ultra-Low Latency 19.38
5 Linear Phase 144 23.14
Low Latency 22.82
Ultra-Low Latency 23.30
6 Linear Phase 27.97
Low Latency 27.45
Ultra-Low Latency 26.46
24.576 768 1 Linear Phase 24 8.01
Low Latency 9.45
Ultra-Low Latency 8.02
2 Linear Phase 48 13.02
Low Latency 13.60
Ultra-Low Latency 13.47
3 Linear Phase 96 16.33
Low Latency 16.60
Ultra-Low Latency 16.69
4 Linear Phase 20.66
Low Latency 22.70
Ultra-Low Latency 22.25
5 Linear Phase 144 25.14
Low Latency 26.46
Ultra-Low Latency 26.18
6 Linear Phase 192 29.94
Low Latency 30.62
Ultra-Low Latency 28.63
48 12.288 256 1 Linear Phase 24 24 9.27
Low Latency 8.72
Ultra-Low Latency 8.41
2 Linear Phase 48 11.85
Low Latency 11.58
Ultra-Low Latency 12.85
3 Linear Phase 96 16.71
Low Latency 15.86
Ultra-Low Latency 16.92
4 Linear Phase 20.88
Low Latency 21.05
Ultra-Low Latency 20.94
5 Linear Phase 144 24.65
Low Latency 22.79
Ultra-Low Latency 23.02
6 Linear Phase 192 32 26.93
Low Latency 28.74
Ultra-Low Latency 26.82
24.576 512 1 Linear Phase 32 32 9.07
Low Latency 8.72
Ultra-Low Latency 9.27
2 Linear Phase 64 13.30
Low Latency 14.31
Ultra-Low Latency 13.82
3 Linear Phase 128 19.15
Low Latency 17.38
Ultra-Low Latency 16.97
4 Linear Phase 20.88
Low Latency 23.07
Ultra-Low Latency 22.72
5 Linear Phase 192 24.73
Low Latency 24.87
Ultra-Low Latency 25.84
6 Linear Phase 28.49
Low Latency 28.74
Ultra-Low Latency 30.60
48 36.864 768 1 Linear Phase 24 24 9.62
Low Latency 8.17
Ultra-Low Latency 7.66
2 Linear Phase 48 14.83
Low Latency 14.27
Ultra-Low Latency 12.52
3 Linear Phase 96 17.65
Low Latency 18.89
Ultra-Low Latency 18.15
4 Linear Phase 23.67
Low Latency 24.07
Ultra-Low Latency 23.05
5 Linear Phase 144 26.94
Low Latency 28.46
Ultra-Low Latency 27.75
6 Linear Phase 192 32 31.00
Low Latency 31.84
Ultra-Low Latency 30.01
96 24.576 256 1 Linear Phase 32 32 11.09
Low Latency 10.84
Ultra-Low Latency 9.48
2 Linear Phase 64 13.52
Low Latency 13.10
Ultra-Low Latency 12.98
3 Linear Phase 128 18.47
Low Latency 17.31
Ultra-Low Latency 19.00
4 Linear Phase 23.06
Low Latency 21.55
Ultra-Low Latency 20.95
5 Linear Phase 192 26.64
Low Latency 24.94
Ultra-Low Latency 26.97
6 Linear Phase 30.36
Low Latency 28.78
Ultra-Low Latency 30.77
36.864 384 1 Linear Phase 24 24 9.49
Low Latency 11.22
Ultra-Low Latency 8.70
2 Linear Phase 48 15.24
Low Latency 16.04
Ultra-Low Latency 14.93
3 Linear Phase 96 21.05
Low Latency 21.13
Ultra-Low Latency 19.03
4 Linear Phase 23.43
Low Latency 23.08
Ultra-Low Latency 25.09
5 Linear Phase 144 27.44
Low Latency 27.94
Ultra-Low Latency 27.54
6 Linear Phase 32.05
Low Latency 32.87
Ultra-Low Latency 32.29
192 12.288 64 1 Linear Phase 24 24 9.44
Low Latency 8.92
Ultra-Low Latency 9.20
2 Linear Phase 48 11.27
Low Latency 11.83
Ultra-Low Latency 13.52
3 Linear Phase 96 15.41
Low Latency 16.34
Ultra-Low Latency 15.52
4 Linear Phase 19.46
5 Linear Phase 144 25.19
Low Latency 24.56
Ultra-Low Latency 24.54
6 Linear Phase 192 32 29.20
Low Latency 28.44
Ultra-Low Latency 27.25

 
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