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  • LMK5B33414 Programmer's Guide

    • SNAU280B July   2022  – March 2025 LMK5B33414

       

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  • LMK5B33414 Programmer's Guide
  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Device Registers
  5. 2Revision History
  6. IMPORTANT NOTICE
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User's Guide

LMK5B33414 Programmer's Guide

Abstract

This programming guide lists the device registers of the LMK5B33414.

Trademarks

All trademarks are the property of their respective owners.

1 Device Registers

Table 1-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in Table 1-1 should be considered as reserved locations and the register contents should not be modified.

Table 1-1 DEVICE Registers
OffsetAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x0R0VNDRID_15:8
0x1R1VNDRID
0x2R2PRODID
0x3R3REVID
0x4R4PRTID_47:40
0x5R5PRTID_39:32
0x6R6PRTID_31:24
0x7R7PRTID_23:16
0x8R8PRTID_15:8
0x9R9PRTID
0x10R16NVMCNT
0x12R18RESERVEDTARGET_ADR_MSB
0x13R19EEREV
0x14R20ROM_PLUS_EEEE_ROM_PAGE_SELRESERVED
0x15R21SPI_3WIRE_DISSYNC_SWRESERVED
0x16R22RESERVEDDPLL3_ENAPLL3_ENDPLL2_ENAPLL2_ENDPLL1_ENAPLL1_EN
0x17R23RESERVEDSWRSTRESERVED
0x18R24RESERVEDAPLL3_STRT_PRTYAPLL2_STRT_PRTYAPLL1_STRT_PRTY
0x19R25RESERVEDSYNC_EN
0x1AR26RESERVEDSYSREF_REQ_MODESYSREF_REQ_SELSYSREF_REQ_SW
0x1BR27TEC_CNTR_39:32
0x1CR28TEC_CNTR_31:24
0x1DR29TEC_CNTR_23:16
0x1ER30TEC_CNTR_15:8
0x1FR31TEC_CNTR
0x20R32RESERVEDTEC_CNTR_TRIG_SELTEC_CNTR_EN
0x21R33RESERVEDLOL_PLL1LOL_PLL2RESERVEDLOS_FDET_XO
0x22R34LOPL_DPLL1LOFL_DPLL1RESERVEDHLDOVR1RESERVED
0x23R35LOPL_DPLL2LOFL_DPLL2RESERVEDHLDOVR2RESERVED
0x24R36LOPL_DPLL3LOFL_DPLL3RESERVEDHLDOVR3RESERVED
0x25R37RESERVEDLOL_PLL1_MASKLOL_PLL2_MASKRESERVEDLOS_FDET_XO_MASK
0x26R38LOPL_DPLL1_MASKLOFL_DPLL1_MASKHIST1_MASKHLDOVR1_MASKREFSWITCH1_MASKLOR_MISSCLK1_MASKLOR_FREQ1_MASKLOR_PH1_MASK
0x27R39LOPL_DPLL2_MASKLOFL_DPLL2_MASKHIST2_MASKHLDOVR2_MASKREFSWITCH2_MASKLOR_MISSCLK2_MASKLOR_FREQ2_MASKLOR_PH2_MASK
0x28R40LOPL_DPLL3_MASKLOFL_DPLL3_MASKHIST3_MASKHLDOVR3_MASKREFSWITCH3_MASKLOR_MISSCLK3_MASKLOR_FREQ3_MASKLOR_PH3_MASK
0x29R41RESERVEDLOL_PLL1_POLLOL_PLL2_POLRESERVEDLOS_FDET_XO_POL
0x2AR42LOPL_DPLL1_POLLOFL_DPLL1_POLHIST1_POLHLDOVR1_POLREFSWITCH1_POLLOR_MISSCLK1_POLLOR_FREQ1_POLLOR_PH1_POL
0x2BR43LOPL_DPLL2_POLLOFL_DPLL2_POLHIST2_POLHLDOVR2_POLREFSWITCH2_POLLOR_MISSCLK2_POLLOR_FREQ2_POLLOR_PH2_POL
0x2CR44LOPL_DPLL3_POLLOFL_DPLL3_POLHIST3_POLHLDOVR3_POLREFSWITCH3_POLLOR_MISSCLK3_POLLOR_FREQ3_POLLOR_PH3_POL
0x2DR45RESERVEDLOL_PLL1_INTRLOL_PLL2_INTRRESERVEDLOS_FDET_XO_INTR
0x2ER46LOPL_DPLL1_INTRLOFL_DPLL1_INTRHIST1_INTRHLDOVR1_INTRREFSWITCH1_INTRLOR_MISSCLK1_INTRLOR_FREQ1_INTRLOR_PH1_INTR
0x2FR47LOPL_DPLL2_INTRLOFL_DPLL2_INTRHIST2_INTRHLDOVR2_INTRREFSWITCH2_INTRLOR_MISSCLK2_INTRLOR_FREQ2_INTRLOR_PH2_INTR
0x30R48LOPL_DPLL3_INTRLOFL_DPLL3_INTRHIST3_INTRHLDOVR3_INTRREFSWITCH3_INTRLOR_MISSCLK3_INTRLOR_FREQ3_INTRLOR_PH3_INTR
0x31R49RESERVEDINT_LATCH_OR_LIVEINT_AND_ORINT_ENINT_CLR
0x32R50RESERVEDREF3_VALID_STATUSREF2_VALID_STATUSREF1_VALID_STATUSREF0_VALID_STATUS
0x33R51RESERVEDREF3_PH_STATUSRESERVEDREF3_FDET_STATUSREF2_PH_STATUSRESERVEDREF2_FDET_STATUS
0x34R52RESERVEDREF1_PH_STATUSRESERVEDREF1_FDET_STATUSREF0_PH_STATUSRESERVEDREF0_FDET_STATUS
0x35R53RESERVEDTEC_CNTR_HELDRESERVED
0x36R54RESERVEDGPIO0_IN_FLT_ENGPIO0_MODE
0x37R55RESERVEDGPIO1_IN_FLT_ENGPIO1_MODE
0x38R56RESERVEDGPIO2_IN_FLT_ENGPIO2_MODE
0x39R57RESERVEDGPIO0_SEL
0x3AR58RESERVEDGPIO1_SEL
0x3BR59RESERVEDGPIO2_SEL
0x3CR60RESERVEDGPIO0_OPENDGPIO1_OPENDGPIO2_OPENDGPIO0_POLGPIO1_POLGPIO2_POL
0x3DR61RESERVEDGPIO_SYSREF_SELMUTE_DPLL3_PHLOCKMUTE_DPLL3_FRLOCK
0x3ER62RESERVEDMUTE_DPLL2_PHLOCKMUTE_DPLL2_FRLOCKMUTE_APLL2_LOCKMUTE_DPLL1_PHLOCKMUTE_DPLL1_FRLOCKMUTE_APLL1_LOCK
0x3FR63RESERVEDXO_FDET_BYPXO_ITYPE
0x40R64RESERVEDXO_OUT_BUF_EN
0x41R65RESERVEDREF3_ITYPE
0x42R66RESERVEDREF2_ITYPE
0x43R67RESERVEDREF1_ITYPE
0x44R68RESERVEDREF0_ITYPE
0x46R70RESERVEDSTATUS_MUX_DIV2_EN
0x4BR75RESERVEDTDC3_ZDM_BYPASS_FB_DIVTDC3_ZDM_FB_PRE_BYPTDC3_IN_SELTDC3_IN_DRV_SEL
0x4CR76RESERVEDTDC2_ZDM_BYPASS_FB_DIVTDC2_ZDM_FB_PRE_BYPTDC2_IN_SELTDC2_IN_DRV_SEL
0x4DR77RESERVEDTDC1_ZDM_BYPASS_FB_DIVTDC1_ZDM_FB_PRE_BYPTDC1_IN_SELTDC1_IN_DRV_SEL
0x4ER78RESERVEDREF_OUT01_ENREF_OUT01_SEL
0x4FR79RESERVEDREF0_EARLY_DET_ENREF0_PH_VALID_ENREF0_VALTMR_ENREF0_PPM_ENREF0_MISSCLK_ENRESERVED
0x50R80RESERVEDREF1_EARLY_DET_ENREF1_PH_VALID_ENREF1_VALTMR_ENREF1_PPM_ENREF1_MISSCLK_ENRESERVED
0x51R81RESERVEDREF2_EARLY_DET_ENREF2_PH_VALID_ENREF2_VALTMR_ENREF2_PPM_ENREF2_MISSCLK_ENRESERVED
0x52R82RESERVEDREF3_EARLY_DET_ENREF3_PH_VALID_ENREF3_VALTMR_ENREF3_PPM_ENREF3_MISSCLK_ENRESERVED
0x53R83REF3_DET_CLK_DIVREF2_DET_CLK_DIVREF1_DET_CLK_DIVREF0_DET_CLK_DIV
0x54R84RESERVEDREF0_MISSCLK_DIV_21:16
0x55R85REF0_MISSCLK_DIV_15:8
0x56R86REF0_MISSCLK_DIV
0x57R87RESERVEDREF1_MISSCLK_DIV_21:16
0x58R88REF1_MISSCLK_DIV_15:8
0x59R89REF1_MISSCLK_DIV
0x5AR90RESERVEDREF2_MISSCLK_DIV_21:16
0x5BR91REF2_MISSCLK_DIV_15:8
0x5CR92REF2_MISSCLK_DIV
0x5DR93RESERVEDREF3_MISSCLK_DIV_21:16
0x5ER94REF3_MISSCLK_DIV_15:8
0x5FR95REF3_MISSCLK_DIV
0x60R96RESERVEDREF0_MISSCLK_VCOSEL
0x61R97RESERVEDREF0_EARLY_CLK_DIV_21:16
0x62R98REF0_EARLY_CLK_DIV_15:8
0x63R99REF0_EARLY_CLK_DIV
0x64R100RESERVEDREF1_EARLY_CLK_DIV_21:16
0x65R101REF1_EARLY_CLK_DIV_15:8
0x66R102REF1_EARLY_CLK_DIV
0x67R103RESERVEDREF2_EARLY_CLK_DIV_21:16
0x68R104REF2_EARLY_CLK_DIV_15:8
0x69R105REF2_EARLY_CLK_DIV
0x6AR106RESERVEDREF3_EARLY_CLK_DIV_21:16
0x6BR107REF3_EARLY_CLK_DIV_15:8
0x6CR108REF3_EARLY_CLK_DIV
0x6DR109RESERVEDREF0_PPM_MIN_14:8
0x6ER110REF0_PPM_MIN
0x6FR111RESERVEDREF0_PPM_MAX_14:8
0x70R112REF0_PPM_MAX
0x71R113RESERVEDREF1_PPM_MIN_14:8
0x72R114REF1_PPM_MIN
0x73R115RESERVEDREF1_PPM_MAX_14:8
0x74R116REF1_PPM_MAX
0x75R117RESERVEDREF2_PPM_MIN_14:8
0x76R118REF2_PPM_MIN
0x77R119RESERVEDREF2_PPM_MAX_14:8
0x78R120REF2_PPM_MAX
0x79R121RESERVEDREF3_PPM_MIN_14:8
0x7AR122REF3_PPM_MIN
0x7BR123RESERVEDREF3_PPM_MAX_14:8
0x7CR124REF3_PPM_MAX
0x8DR141RESERVEDREF2_PH_VALID_CNT_MSBREF2_CNTSTRT_27:24
0x8ER142REF2_CNTSTRT_23:16
0x8FR143REF2_CNTSTRT_15:8
0x90R144REF2_CNTSTRT
0x91R145RESERVEDREF2_HOLD_CNTSTRT_27:24
0x92R146REF2_HOLD_CNTSTRT_23:16
0x93R147REF2_HOLD_CNTSTRT_15:8
0x94R148REF2_HOLD_CNTSTRT
0x95R149RESERVEDREF3_PH_VALID_CNT_MSBREF3_CNTSTRT_27:24
0x96R150REF3_CNTSTRT_23:16
0x97R151REF3_CNTSTRT_15:8
0x98R152REF3_CNTSTRT
0x99R153RESERVEDREF3_HOLD_CNTSTRT_27:24
0x9AR154REF3_HOLD_CNTSTRT_23:16
0x9BR155REF3_HOLD_CNTSTRT_15:8
0x9CR156REF3_HOLD_CNTSTRT
0x9DR157RESERVEDREF0VLDTMR
0x9ER158RESERVEDREF1VLDTMR
0x9FR159RESERVEDREF2VLDTMR
0xA0R160RESERVEDREF3VLDTMR
0xA1R161RESERVEDREF0_PH_VALID_THR_13:8
0xA2R162REF0_PH_VALID_THR
0xA3R163RESERVEDREF1_PH_VALID_THR_13:8
0xA4R164REF1_PH_VALID_THR
0xA5R165RESERVEDREF2_PH_VALID_THR_13:8
0xA6R166REF2_PH_VALID_THR
0xA7R167RESERVEDREF3_PH_VALID_THR_13:8
0xA8R168REF3_PH_VALID_THR
0xAAR170NVMSCRC
0xABR171RESERVEDREGCOMMITNVMCRCERRRESERVEDNVMBUSYNVMERASENVMPROG
0xACR172NVMLCRC
0xADR173RESERVEDMEMADR_12:8
0xAER174MEMADR
0xAFR175NVMDAT
0xB0R176RAMDAT
0xB4R180NVMUNLK
0xDFR223RESERVEDDPLL1_REF0_AUTO_PRTYDPLL1_REF1_AUTO_PRTY
0xE0R224RESERVEDDPLL1_REF2_AUTO_PRTYDPLL1_REF3_AUTO_PRTY
0xE1R225RESERVEDDPLL1_REF4_AUTO_PRTYDPLL1_REF5_AUTO_PRTY
0xE2R226RESERVEDDPLL1_MAN_REFSELDPLL1_MAN_SWITCH_PIN_MODEDPLL1_SWITCH_MODE
0xE3R227RESERVEDDPLL1_REFSEL_STAT
0xE4R228DPLL1_LOCKDET_PPM_ENDPLL1_LOCKDET_PPM_MAX_14:8
0xE5R229DPLL1_LOCKDET_PPM_MAX
0xE6R230RESERVEDDPLL1_UNLOCKDET_PPM_MAX_14:8
0xE7R231DPLL1_UNLOCKDET_PPM_MAX
0xE8R232RESERVEDDPLL1_LOCKDET2_PPM_CNTSTRT_29:24
0xE9R233DPLL1_LOCKDET2_PPM_CNTSTRT_23:16
0xEAR234DPLL1_LOCKDET2_PPM_CNTSTRT_15:8
0xEBR235DPLL1_LOCKDET2_PPM_CNTSTRT
0xECR236RESERVEDDPLL1_LOCKDET_PPM_CNTSTRT_29:24
0xEDR237DPLL1_LOCKDET_PPM_CNTSTRT_23:16
0xEER238DPLL1_LOCKDET_PPM_CNTSTRT_15:8
0xEFR239DPLL1_LOCKDET_PPM_CNTSTRT
0xF0R240RESERVEDDPLL1_LOCKDET_VCO_PPM_CNTSTRT_29:24
0xF1R241DPLL1_LOCKDET_VCO_PPM_CNTSTRT_23:16
0xF2R242DPLL1_LOCKDET_VCO_PPM_CNTSTRT_15:8
0xF3R243DPLL1_LOCKDET_VCO_PPM_CNTSTRT
0xF4R244RESERVEDDPLL1_STATUS_PPM_LOCK
0xF7R247DPLL1_LOOP_ENDPLL1_PHASE_CANCEL_ENRESERVEDDPLL1_PHS1_ENDPLL1_ZDM_ENDPLL1_HIST_ENDPLL1_PHASE_CANCEL_ALWAYSRESERVED
0xF8R248DPLL1_HOLD_SLEW_LIM_ENRESERVEDDPLL1_CLK_DIV_SRC_SELRESERVED
0xFAR250RESERVEDDPLL1_PH_OFFSET_44:40
0xFBR251DPLL1_PH_OFFSET_39:32
0xFCR252DPLL1_PH_OFFSET_31:24
0xFDR253DPLL1_PH_OFFSET_23:16
0xFER254DPLL1_PH_OFFSET_15:8
0xFFR255DPLL1_PH_OFFSET
0x100R256DPLL1_FREE_RUN_39:32
0x101R257DPLL1_FREE_RUN_31:24
0x102R258DPLL1_FREE_RUN_23:16
0x103R259DPLL1_FREE_RUN_15:8
0x104R260DPLL1_FREE_RUN
0x105R261RESERVEDDPLL1_1PPS_MODEDPLL1_1PPS_ENRESERVED
0x122R290RESERVEDDPLL1_LCK_TIMER_9:8
0x123R291DPLL1_LCK_TIMER
0x124R292RESERVEDDPLL1_HIST_TIMER_9:8
0x125R293DPLL1_HIST_TIMER
0x126R294RESERVEDDPLL1_HOLD_TIMER_9:8
0x127R295DPLL1_HOLD_TIMER
0x128R296RESERVEDDPLL1_PHS1_TIMER_9:8
0x129R297DPLL1_PHS1_TIMER
0x12ER302RESERVEDDPLL1_HIST_GAIN
0x12FR303RESERVEDDPLL1_PL_THRESH
0x130R304RESERVEDDPLL1_PL_UNLK_THRESH
0x131R305RESERVEDDPLL1_PHS1_THRESH
0x134R308RESERVEDDPLL1_HOLD_SLEW_STEP
0x136R310RESERVEDDPLL1_STATUS_PLRESERVED
0x137R311RESERVEDDPLL1_DCO_SLEW_ACTIVERESERVED
0x13AR314RESERVEDDPLL1_FB_DIV_32:32
0x13BR315DPLL1_FB_DIV_31:24
0x13CR316DPLL1_FB_DIV_23:16
0x13DR317DPLL1_FB_DIV_15:8
0x13ER318DPLL1_FB_DIV
0x13FR319DPLL1_FB_NUM_39:32
0x140R320DPLL1_FB_NUM_31:24
0x141R321DPLL1_FB_NUM_23:16
0x142R322DPLL1_FB_NUM_15:8
0x143R323DPLL1_FB_NUM
0x144R324DPLL1_FB_DEN_39:32
0x145R325DPLL1_FB_DEN_31:24
0x146R326DPLL1_FB_DEN_23:16
0x147R327DPLL1_FB_DEN_15:8
0x148R328DPLL1_FB_DEN
0x149R329RESERVEDDPLL1_FB2_DIV_32:32
0x14AR330DPLL1_FB2_DIV_31:24
0x14BR331DPLL1_FB2_DIV_23:16
0x14CR332DPLL1_FB2_DIV_15:8
0x14DR333DPLL1_FB2_DIV
0x14ER334DPLL1_FB2_NUM_39:32
0x14FR335DPLL1_FB2_NUM_31:24
0x150R336DPLL1_FB2_NUM_23:16
0x151R337DPLL1_FB2_NUM_15:8
0x152R338DPLL1_FB2_NUM
0x153R339DPLL1_FB2_DEN_39:32
0x154R340DPLL1_FB2_DEN_31:24
0x155R341DPLL1_FB2_DEN_23:16
0x156R342DPLL1_FB2_DEN_15:8
0x157R343DPLL1_FB2_DEN
0x158R344RESERVEDDPLL1_REF5_FB_SELDPLL1_REF4_FB_SELDPLL1_REF3_FB_SELDPLL1_REF2_FB_SELDPLL1_REF1_FB_SELDPLL1_REF0_FB_SEL
0x159R345RESERVEDDPLL1_FB_MASH_ORDER
0x15AR346RESERVEDDPLL1_FB_FDEV_37:32
0x15BR347DPLL1_FB_FDEV_31:24
0x15CR348DPLL1_FB_FDEV_23:16
0x15DR349DPLL1_FB_FDEV_15:8
0x15ER350DPLL1_FB_FDEV
0x15FR351RESERVEDDPLL1_FB_FDEV_UPDATE
0x160R352RESERVEDDPLL1_FB_FDEV_EN
0x161R353DPLL1_FB_NUM_STAT_39:32
0x162R354DPLL1_FB_NUM_STAT_31:24
0x163R355DPLL1_FB_NUM_STAT_23:16
0x164R356DPLL1_FB_NUM_STAT_15:8
0x165R357DPLL1_FB_NUM_STAT
0x166R358RESERVEDDPLL1_REF0_DBLR_ENDPLL1_REF1_DBLR_ENDPLL1_REF2_DBLR_ENDPLL1_REF3_DBLR_EN
0x167R359DPLL1_REF0_RDIV_15:8
0x168R360DPLL1_REF0_RDIV
0x169R361DPLL1_REF1_RDIV_15:8
0x16AR362DPLL1_REF1_RDIV
0x16BR363DPLL1_REF2_RDIV_15:8
0x16CR364DPLL1_REF2_RDIV
0x16DR365DPLL1_REF3_RDIV_15:8
0x16ER366DPLL1_REF3_RDIV
0x16FR367DPLL1_REF4_RDIV_15:8
0x170R368DPLL1_REF4_RDIV
0x171R369DPLL1_REF5_RDIV_15:8
0x172R370DPLL1_REF5_RDIV
0x175R373RESERVEDDPLL2_REF0_AUTO_PRTYDPLL2_REF1_AUTO_PRTY
0x176R374RESERVEDDPLL2_REF2_AUTO_PRTYDPLL2_REF3_AUTO_PRTY
0x177R375RESERVEDDPLL2_REF4_AUTO_PRTYDPLL2_REF5_AUTO_PRTY
0x178R376RESERVEDDPLL2_MAN_REFSELDPLL2_MAN_SWITCH_PIN_MODEDPLL2_SWITCH_MODE
0x179R377RESERVEDDPLL2_REFSEL_STAT
0x17AR378DPLL2_LOCKDET_PPM_ENDPLL2_LOCKDET_PPM_MAX_14:8
0x17BR379DPLL2_LOCKDET_PPM_MAX
0x17CR380RESERVEDDPLL2_UNLOCKDET_PPM_MAX_14:8
0x17DR381DPLL2_UNLOCKDET_PPM_MAX
0x17ER382RESERVEDDPLL2_LOCKDET2_PPM_CNTSTRT_29:24
0x17FR383DPLL2_LOCKDET2_PPM_CNTSTRT_23:16
0x180R384DPLL2_LOCKDET2_PPM_CNTSTRT_15:8
0x181R385DPLL2_LOCKDET2_PPM_CNTSTRT
0x182R386RESERVEDDPLL2_LOCKDET_PPM_CNTSTRT_29:24
0x183R387DPLL2_LOCKDET_PPM_CNTSTRT_23:16
0x184R388DPLL2_LOCKDET_PPM_CNTSTRT_15:8
0x185R389DPLL2_LOCKDET_PPM_CNTSTRT
0x186R390RESERVEDDPLL2_LOCKDET_VCO_PPM_CNTSTRT_29:24
0x187R391DPLL2_LOCKDET_VCO_PPM_CNTSTRT_23:16
0x188R392DPLL2_LOCKDET_VCO_PPM_CNTSTRT_15:8
0x189R393DPLL2_LOCKDET_VCO_PPM_CNTSTRT
0x18AR394RESERVEDDPLL2_STATUS_PPM_LOCK
0x18DR397DPLL2_LOOP_ENDPLL2_PHASE_CANCEL_ENRESERVEDDPLL2_PHS1_ENDPLL2_ZDM_ENDPLL2_HIST_ENDPLL2_PHASE_CANCEL_ALWAYSRESERVED
0x18ER398DPLL2_HOLD_SLEW_LIM_ENRESERVED
0x190R400RESERVEDDPLL2_PH_OFFSET_44:40
0x191R401DPLL2_PH_OFFSET_39:32
0x192R402DPLL2_PH_OFFSET_31:24
0x193R403DPLL2_PH_OFFSET_23:16
0x194R404DPLL2_PH_OFFSET_15:8
0x195R405DPLL2_PH_OFFSET
0x196R406DPLL2_FREE_RUN_39:32
0x197R407DPLL2_FREE_RUN_31:24
0x198R408DPLL2_FREE_RUN_23:16
0x199R409DPLL2_FREE_RUN_15:8
0x19AR410DPLL2_FREE_RUN
0x19BR411RESERVEDDPLL2_1PPS_MODEDPLL2_1PPS_ENRESERVED
0x1B8R440RESERVEDDPLL2_LCK_TIMER_9:8
0x1B9R441DPLL2_LCK_TIMER
0x1BAR442RESERVEDDPLL2_HIST_TIMER_9:8
0x1BBR443DPLL2_HIST_TIMER
0x1BCR444RESERVEDDPLL2_HOLD_TIMER_9:8
0x1BDR445DPLL2_HOLD_TIMER
0x1BER446RESERVEDDPLL2_PHS1_TIMER_9:8
0x1BFR447DPLL2_PHS1_TIMER
0x1C4R452RESERVEDDPLL2_HIST_GAIN
0x1C5R453RESERVEDDPLL2_PL_THRESH
0x1C6R454RESERVEDDPLL2_PL_UNLK_THRESH
0x1C7R455RESERVEDDPLL2_PHS1_THRESH
0x1CAR458RESERVEDDPLL2_HOLD_SLEW_STEP
0x1CCR460RESERVEDDPLL2_STATUS_PLRESERVED
0x1CDR461RESERVEDDPLL2_DCO_SLEW_ACTIVERESERVED
0x1D0R464RESERVEDDPLL2_FB_DIV_32:32
0x1D1R465DPLL2_FB_DIV_31:24
0x1D2R466DPLL2_FB_DIV_23:16
0x1D3R467DPLL2_FB_DIV_15:8
0x1D4R468DPLL2_FB_DIV
0x1D5R469DPLL2_FB_NUM_39:32
0x1D6R470DPLL2_FB_NUM_31:24
0x1D7R471DPLL2_FB_NUM_23:16
0x1D8R472DPLL2_FB_NUM_15:8
0x1D9R473DPLL2_FB_NUM
0x1DAR474DPLL2_FB_DEN_39:32
0x1DBR475DPLL2_FB_DEN_31:24
0x1DCR476DPLL2_FB_DEN_23:16
0x1DDR477DPLL2_FB_DEN_15:8
0x1DER478DPLL2_FB_DEN
0x1DFR479RESERVEDDPLL2_FB2_DIV_32:32
0x1E0R480DPLL2_FB2_DIV_31:24
0x1E1R481DPLL2_FB2_DIV_23:16
0x1E2R482DPLL2_FB2_DIV_15:8
0x1E3R483DPLL2_FB2_DIV
0x1E4R484DPLL2_FB2_NUM_39:32
0x1E5R485DPLL2_FB2_NUM_31:24
0x1E6R486DPLL2_FB2_NUM_23:16
0x1E7R487DPLL2_FB2_NUM_15:8
0x1E8R488DPLL2_FB2_NUM
0x1E9R489DPLL2_FB2_DEN_39:32
0x1EAR490DPLL2_FB2_DEN_31:24
0x1EBR491DPLL2_FB2_DEN_23:16
0x1ECR492DPLL2_FB2_DEN_15:8
0x1EDR493DPLL2_FB2_DEN
0x1EER494RESERVEDDPLL2_REF5_FB_SELDPLL2_REF4_FB_SELDPLL2_REF3_FB_SELDPLL2_REF2_FB_SELDPLL2_REF1_FB_SELDPLL2_REF0_FB_SEL
0x1EFR495RESERVEDDPLL2_FB_MASH_ORDER
0x1F0R496RESERVEDDPLL2_FB_FDEV_37:32
0x1F1R497DPLL2_FB_FDEV_31:24
0x1F2R498DPLL2_FB_FDEV_23:16
0x1F3R499DPLL2_FB_FDEV_15:8
0x1F4R500DPLL2_FB_FDEV
0x1F5R501RESERVEDDPLL2_FB_FDEV_UPDATE
0x1F6R502RESERVEDDPLL2_FB_FDEV_EN
0x1F7R503DPLL2_FB_NUM_STAT_39:32
0x1F8R504DPLL2_FB_NUM_STAT_31:24
0x1F9R505DPLL2_FB_NUM_STAT_23:16
0x1FAR506DPLL2_FB_NUM_STAT_15:8
0x1FBR507DPLL2_FB_NUM_STAT
0x1FCR508RESERVEDDPLL2_REF0_DBLR_ENDPLL2_REF1_DBLR_ENDPLL2_REF2_DBLR_ENDPLL2_REF3_DBLR_EN
0x1FDR509DPLL2_REF0_RDIV_15:8
0x1FER510DPLL2_REF0_RDIV
0x1FFR511DPLL2_REF1_RDIV_15:8
0x200R512DPLL2_REF1_RDIV
0x201R513DPLL2_REF2_RDIV_15:8
0x202R514DPLL2_REF2_RDIV
0x203R515DPLL2_REF3_RDIV_15:8
0x204R516DPLL2_REF3_RDIV
0x205R517DPLL2_REF4_RDIV_15:8
0x206R518DPLL2_REF4_RDIV
0x207R519DPLL2_REF5_RDIV_15:8
0x208R520DPLL2_REF5_RDIV
0x20BR523RESERVEDDPLL3_REF0_AUTO_PRTYDPLL3_REF1_AUTO_PRTY
0x20CR524RESERVEDDPLL3_REF2_AUTO_PRTYDPLL3_REF3_AUTO_PRTY
0x20DR525RESERVEDDPLL3_REF4_AUTO_PRTYDPLL3_REF5_AUTO_PRTY
0x20ER526RESERVEDDPLL3_MAN_REFSELDPLL3_MAN_SWITCH_PIN_MODEDPLL3_SWITCH_MODE
0x20FR527RESERVEDDPLL3_REFSEL_STAT
0x210R528DPLL3_LOCKDET_PPM_ENDPLL3_LOCKDET_PPM_MAX_14:8
0x211R529DPLL3_LOCKDET_PPM_MAX
0x212R530RESERVEDDPLL3_UNLOCKDET_PPM_MAX_14:8
0x213R531DPLL3_UNLOCKDET_PPM_MAX
0x214R532RESERVEDDPLL3_LOCKDET2_PPM_CNTSTRT_29:24
0x215R533DPLL3_LOCKDET2_PPM_CNTSTRT_23:16
0x216R534DPLL3_LOCKDET2_PPM_CNTSTRT_15:8
0x217R535DPLL3_LOCKDET2_PPM_CNTSTRT
0x218R536RESERVEDDPLL3_LOCKDET_PPM_CNTSTRT_29:24
0x219R537DPLL3_LOCKDET_PPM_CNTSTRT_23:16
0x21AR538DPLL3_LOCKDET_PPM_CNTSTRT_15:8
0x21BR539DPLL3_LOCKDET_PPM_CNTSTRT
0x21CR540RESERVEDDPLL3_LOCKDET_VCO_PPM_CNTSTRT_29:24
0x21DR541DPLL3_LOCKDET_VCO_PPM_CNTSTRT_23:16
0x21ER542DPLL3_LOCKDET_VCO_PPM_CNTSTRT_15:8
0x21FR543DPLL3_LOCKDET_VCO_PPM_CNTSTRT
0x220R544RESERVEDDPLL3_STATUS_PPM_LOCK
0x223R547DPLL3_LOOP_ENDPLL3_PHASE_CANCEL_ENDPLL3_FASTLOCK_ALWAYSDPLL3_PHS1_ENDPLL3_ZDM_ENDPLL3_HIST_ENDPLL3_PHASE_CANCEL_ALWAYSRESERVED
0x224R548DPLL3_HOLD_SLEW_LIM_ENRESERVED
0x226R550RESERVEDDPLL3_PH_OFFSET_44:40
0x227R551DPLL3_PH_OFFSET_39:32
0x228R552DPLL3_PH_OFFSET_31:24
0x229R553DPLL3_PH_OFFSET_23:16
0x22AR554DPLL3_PH_OFFSET_15:8
0x22BR555DPLL3_PH_OFFSET
0x22CR556DPLL3_FREE_RUN_39:32
0x22DR557DPLL3_FREE_RUN_31:24
0x22ER558DPLL3_FREE_RUN_23:16
0x22FR559DPLL3_FREE_RUN_15:8
0x230R560DPLL3_FREE_RUN
0x231R561DPLL3_PPM_REF_SELDPLL3_1PPS_MODEDPLL3_1PPS_ENRESERVED
0x24ER590RESERVEDDPLL3_LCK_TIMER_9:8
0x24FR591DPLL3_LCK_TIMER
0x250R592RESERVEDDPLL3_HIST_TIMER_9:8
0x251R593DPLL3_HIST_TIMER
0x252R594RESERVEDDPLL3_HOLD_TIMER_9:8
0x253R595DPLL3_HOLD_TIMER
0x254R596RESERVEDDPLL3_PHS1_TIMER_9:8
0x255R597DPLL3_PHS1_TIMER
0x25AR602RESERVEDDPLL3_HIST_GAIN
0x25BR603RESERVEDDPLL3_PL_THRESH
0x25CR604RESERVEDDPLL3_PL_UNLK_THRESH
0x25DR605RESERVEDDPLL3_PHS1_THRESH
0x262R610RESERVEDDPLL3_STATUS_PLRESERVED
0x263R611RESERVEDDPLL3_DCO_SLEW_ACTIVERESERVED
0x266R614RESERVEDDPLL3_FB_DIV_32:32
0x267R615DPLL3_FB_DIV_31:24
0x268R616DPLL3_FB_DIV_23:16
0x269R617DPLL3_FB_DIV_15:8
0x26AR618DPLL3_FB_DIV
0x26BR619DPLL3_FB_NUM_39:32
0x26CR620DPLL3_FB_NUM_31:24
0x26DR621DPLL3_FB_NUM_23:16
0x26ER622DPLL3_FB_NUM_15:8
0x26FR623DPLL3_FB_NUM
0x270R624DPLL3_FB_DEN_39:32
0x271R625DPLL3_FB_DEN_31:24
0x272R626DPLL3_FB_DEN_23:16
0x273R627DPLL3_FB_DEN_15:8
0x274R628DPLL3_FB_DEN
0x275R629RESERVEDDPLL3_FB2_DIV_32:32
0x276R630DPLL3_FB2_DIV_31:24
0x277R631DPLL3_FB2_DIV_23:16
0x278R632DPLL3_FB2_DIV_15:8
0x279R633DPLL3_FB2_DIV
0x27AR634DPLL3_FB2_NUM_39:32
0x27BR635DPLL3_FB2_NUM_31:24
0x27CR636DPLL3_FB2_NUM_23:16
0x27DR637DPLL3_FB2_NUM_15:8
0x27ER638DPLL3_FB2_NUM
0x27FR639DPLL3_FB2_DEN_39:32
0x280R640DPLL3_FB2_DEN_31:24
0x281R641DPLL3_FB2_DEN_23:16
0x282R642DPLL3_FB2_DEN_15:8
0x283R643DPLL3_FB2_DEN
0x284R644RESERVEDDPLL3_REF5_FB_SELDPLL3_REF4_FB_SELDPLL3_REF3_FB_SELDPLL3_REF2_FB_SELDPLL3_REF1_FB_SELDPLL3_REF0_FB_SEL
0x285R645RESERVEDDPLL3_FB_MASH_ORDER
0x286R646RESERVEDDPLL3_FB_FDEV_37:32
0x287R647DPLL3_FB_FDEV_31:24
0x288R648DPLL3_FB_FDEV_23:16
0x289R649DPLL3_FB_FDEV_15:8
0x28AR650DPLL3_FB_FDEV
0x28BR651RESERVEDDPLL3_FB_FDEV_UPDATE
0x28CR652RESERVEDDPLL3_FB_FDEV_EN
0x28DR653DPLL3_FB_NUM_STAT_39:32
0x28ER654DPLL3_FB_NUM_STAT_31:24
0x28FR655DPLL3_FB_NUM_STAT_23:16
0x290R656DPLL3_FB_NUM_STAT_15:8
0x291R657DPLL3_FB_NUM_STAT
0x292R658RESERVEDDPLL3_REF0_DBLR_ENDPLL3_REF1_DBLR_ENDPLL3_REF2_DBLR_ENDPLL3_REF3_DBLR_EN
0x293R659DPLL3_REF0_RDIV_15:8
0x294R660DPLL3_REF0_RDIV
0x295R661DPLL3_REF1_RDIV_15:8
0x296R662DPLL3_REF1_RDIV
0x297R663DPLL3_REF2_RDIV_15:8
0x298R664DPLL3_REF2_RDIV
0x299R665DPLL3_REF3_RDIV_15:8
0x29AR666DPLL3_REF3_RDIV
0x29BR667DPLL3_REF4_RDIV_15:8
0x29CR668DPLL3_REF4_RDIV
0x29DR669DPLL3_REF5_RDIV_15:8
0x29ER670DPLL3_REF5_RDIV
0x2C3R707PLL1_CP_PU_R
0x2C4R708RESERVEDPLL1_CPG
0x2C5R709RESERVEDPLL1_LF_R2
0x2C6R710RESERVEDPLL1_LF_R3
0x2C7R711RESERVEDPLL1_LF_R4
0x2C8R712PLL1_DISABLE_3RD4THPLL1_LF_C3PLL1_LF_C4
0x2C9R713RESERVEDPLL1_RDIV_8:8
0x2CAR714PLL1_RDIV
0x2CBR715RESERVEDPLL1_RDIV_XO_ENPLL1_RDIV_XO_DBLR_ENPLL1_RDIV_BYPASS_ENPLL1_RDIV_MUX_SEL
0x2CCR716RESERVEDPLL1_NDIV_8:8
0x2CDR717PLL1_NDIV
0x2CER718PLL1_NUM_MSB
0x2CFR719PLL1_NUM_39:32
0x2D0R720PLL1_NUM_31:24
0x2D1R721PLL1_NUM_23:16
0x2D2R722PLL1_NUM_15:8
0x2D3R723PLL1_NUM
0x2D4R724RESERVEDPLL1_DTHRMODEPLL1_ORDERPLL1_MODE
0x2D5R725APLL1_NUM_STAT_39:32
0x2D6R726APLL1_NUM_STAT_31:24
0x2D7R727APLL1_NUM_STAT_23:16
0x2D8R728APLL1_NUM_STAT_15:8
0x2D9R729APLL1_NUM_STAT
0x2DBR731PLL1_PRI_DIV_SYNC_ENPLL1_PRI_DIV_ENPLL1_PRI_DIVPLL1_P1_DIV_OUT0_1_ENPLL1_P1_DIV_OUT2_3_ENPLL1_P1_DIV_OUT14_15_EN
0x2DCR732PLL1_SEC_DIV_SYNC_ENPLL1_SEC_DIV_ENPLL1_SEC_DIVPLL1_P2_DIV_OUT0_1_ENRESERVED
0x2DDR733PLL1_VCO_BUF_ENPLL1_VCO_BUF_2REF_ENPLL1_VCO_BUF_2DPLL_ENRESERVEDPLL1_VCO_BUF_PPM_CHECK_ENPLL1_VCO_BUF_FB_TDC_EN
0x2E0R736PLL1_NCLK_TEST_ENRESERVEDPLL1_RDIV_OUTPUT_ENRESERVED
0x2E5R741RESERVEDPLL1_VM_INSIDEPLL1_VM_HIRESERVED
0x2E9R745RESERVEDPLL1_NDIV_OUTPUT_ENRESERVED
0x2EAR746RESERVEDPLL1_VCO_PREBUF_EN
0x305R773RESERVED
0x309R777PLL2_CP_PU_R
0x30AR778RESERVEDPLL2_CP_PU_DISPLL2_CPG
0x30BR779PLL2_LF_R2
0x30CR780RESERVEDPLL2_LF_R3
0x30DR781RESERVEDPLL2_LF_R4
0x30ER782PLL2_DISABLE_3RD4THPLL2_LF_C3PLL2_LF_C4
0x30FR783RESERVEDPLL2_RDIV_8:8
0x310R784PLL2_RDIV
0x311R785RESERVEDPLL2_RDIV_XO_ENPLL2_RDIV_XO_DBLR_ENPLL2_RDIV_BYPASS_ENPLL2_RDIV_MUX_SEL
0x312R786RESERVEDPLL2_NDIV_8:8
0x313R787PLL2_NDIV
0x314R788PLL2_NUM_MSB
0x315R789PLL2_NUM_39:32
0x316R790PLL2_NUM_31:24
0x317R791PLL2_NUM_23:16
0x318R792PLL2_NUM_15:8
0x319R793PLL2_NUM
0x31AR794RESERVEDPLL2_DTHRMODEPLL2_ORDERPLL2_MODE
0x31BR795APLL2_NUM_STAT_39:32
0x31CR796APLL2_NUM_STAT_31:24
0x31DR797APLL2_NUM_STAT_23:16
0x31ER798APLL2_NUM_STAT_15:8
0x31FR799APLL2_NUM_STAT
0x323R803RESERVEDPLL2_VCO_BUF_ENPLL2_VCO_BUF_2REF_ENPLL2_VCO_BUF_2DPLL_ENPLL2_VCO_BUF_2WNDDET_EN
0x324R804RESERVEDPLL2_VCO_DIV_SYNC_ENPLL2_VCO_DIV_ENPLL2_VCO_DIV
0x325R805RESERVEDPLL2_VCO_BUF_FB_TDC_ENPLL2_P1_OUT14_15_ENPLL2_P1_OUT8_13_ENPLL2_P1_OUT4_7_ENPLL2_P1_OUT2_3_ENPLL2_P1_OUT0_1_EN
0x328R808RESERVEDPLL2_RDIV_OUTPUT_ENRESERVED
0x32DR813RESERVEDPLL2_VM_INSIDEPLL2_VM_HIRESERVED
0x332R818RESERVEDPLL2_NDIV_OUTPUT_ENRESERVED
0x333R819RESERVEDPLL2_VCO_PREBUF_EN
0x348R840PLL3_CPBAW_BLEED
0x349R841RESERVEDPLL3_CP_PU_DISPLL3_CPG
0x34AR842RESERVEDPLL3_LF_R2
0x34BR843RESERVEDPLL3_LF_R3
0x34CR844RESERVEDPLL3_LF_R4
0x34DR845RESERVEDPLL3_LF_C3PLL3_LF_C4
0x34ER846RESERVEDPLL3_RDIV_8:8
0x34FR847PLL3_RDIV
0x350R848RESERVEDPLL3_RDIV_XO_ENPLL3_RDIV_XO_DBLR_ENPLL3_RDIV_BYPASS_ENPLL3_RDIV_MUX_SEL
0x351R849RESERVEDPLL3_NDIV_8:8
0x352R850PLL3_NDIV
0x353R851PLL3_NUM_MSB
0x354R852PLL3_NUM_39:32
0x355R853PLL3_NUM_31:24
0x356R854PLL3_NUM_23:16
0x357R855PLL3_NUM_15:8
0x358R856PLL3_NUM
0x359R857RESERVEDPLL3_DTHRMODEPLL3_ORDERPLL3_MODE
0x35AR858APLL3_NUM_STAT_39:32
0x35BR859APLL3_NUM_STAT_31:24
0x35CR860APLL3_NUM_STAT_23:16
0x35DR861APLL3_NUM_STAT_15:8
0x35ER862APLL3_NUM_STAT
0x360R864PLL3_VCO_BUF_OUT_ENPLL3_VCO_DIV_SYNC_ENPLL3_PRI_DIV
0x361R865PLL3_VCO_DIV_SELPLL3_VCO_CHAN_DRVR_IN_ENPLL3_P1_OUT14_15_ENPLL3_P1_OUT8_13_ENPLL3_P1_OUT4_7_ENPLL3_P1_OUT2_3_ENPLL3_P1_OUT0_1_EN
0x362R866RESERVEDPLL3_VCO_BUF_2REF_ENPLL3_WIN_DET_DRVR_ENPLL3_VCO_BUF_FB_TDC_EN
0x368R872RESERVEDPLL3_RDIV_OUTPUT_ENRESERVED
0x372R882RESERVEDPLL3_NDIV_OUTPUT_ENRESERVED
0x3C1R961RESERVEDOUT_0_ENOUT_0_FMT
0x3C2R962OUT_0_CAP_ENOUT_0_STATIC_LOWOUT_0_P_CMOS_ENOUT_0_N_CMOS_ENOUT_0_P_INVERT_POLARITYOUT_0_N_INVERT_POLARITYOUT_0_P_FORCELOWOUT_0_N_FORCELOW
0x3C3R963OUT_0_CONFIGURATION
0x3C4R964RESERVEDOUT_1_ENOUT_1_FMT
0x3C5R965OUT_1_CAP_ENOUT_1_STATIC_LOWOUT_1_P_CMOS_ENOUT_1_N_CMOS_ENOUT_1_P_INVERT_POLARITYOUT_1_N_INVERT_POLARITYOUT_1_P_FORCELOWOUT_1_N_FORCELOW
0x3C6R966OUT_1_CONFIGURATION
0x3C7R967RESERVEDOUT_0_1_CMOS_OUT_VOLTAGE_SELOUT_0_1_CMOS_OUT_LDO_EN
0x3C8R968RESERVEDOUT_0_1_ZDM_TDC_SELOUT_0_1_ZDM_EN
0x3C9R969RESERVEDOUT_0_1_DIV_MUTE_ENOUT_0_1_DIV_SYNC_ENOUT_0_1_SR_DIV_SYNC_ENOUT_0_1_CH0_CHAN_POL_SELOUT_0_1_CH1_CHAN_POL_SELOUT_0_1_CH0_DIV_ENOUT_0_1_CH1_DIV_EN
0x3CCR972RESERVEDOUT_0_1_CH0_CH_DIV_SR_MUX_CLK_SELRESERVED
0x3CDR973OUT_0_1_CLK_IN_FANOUTRESERVED
0x3CER974RESERVEDOUT_0_1_CH0_CH_STATIC_OFFSET_11:8
0x3CFR975OUT_0_1_CH0_CH_STATIC_OFFSET
0x3D0R976RESERVEDOUT_0_1_CH1_CH_STATIC_OFFSET_11:8
0x3D1R977OUT_0_1_CH1_CH_STATIC_OFFSET
0x3D2R978RESERVEDOUT_0_1_CH0_CH_DIV_11:8
0x3D3R979OUT_0_1_CH0_CH_DIV
0x3D4R980RESERVEDOUT_0_1_CH1_CH_DIV_11:8
0x3D5R981OUT_0_1_CH1_CH_DIV
0x3D6R982RESERVEDOUT_0_1_SR_ANA_DELAY
0x3D7R983RESERVEDOUT_0_1_SR_ANA_DELAY_DIV2_SELOUT_0_1_SR_ANA_DELAY_ENOUT_0_1_SR_ANA_DELAY_SMALL_STEP_ENOUT_0_1_SR_ANA_DELAY_RANGE
0x3D8R984RESERVEDOUT_0_1_SR_DDLY
0x3D9R985RESERVEDOUT_0_1_SR_DIV_19:16
0x3DAR986OUT_0_1_SR_DIV_15:8
0x3DBR987OUT_0_1_SR_DIV
0x3DCR988RESERVEDOUT_0_1_SR_DIV_STATIC_OFFSET_14:8
0x3DDR989OUT_0_1_SR_DIV_STATIC_OFFSET
0x3DER990OUT_0_1_SR_REQ_MODEOUT_0_1_SR_GPIO_ENRESERVEDOUT_0_1_PULSE_COUNTOUT_0_1_SR_MODE
0x3DFR991RESERVEDOUT_0_1_SR_CH0_DIV_BYPASSRESERVED
0x400R1024RESERVEDOUT_2_ENOUT_2_FMT
0x401R1025RESERVEDOUT_2_CAP_ENOUT_2_CONFIGURATION
0x402R1026OUT_2_CHAN_POL_SELOUT_2_CLK_MUXRESERVEDOUT_2_DIV_ENOUT_2_CH_MUX_SEL
0x403R1027RESERVEDOUT_2_MUTE_ENOUT_2_SYNC_ENRESERVED
0x404R1028RESERVEDOUT_2_CH_STATIC_OFFSET_11:8
0x405R1029OUT_2_CH_STATIC_OFFSET
0x406R1030RESERVEDOUT_2_CH_DIV_11:8
0x407R1031OUT_2_CH_DIV
0x420R1056RESERVEDOUT_3_ENOUT_3_FMT
0x421R1057RESERVEDOUT_3_CAP_ENOUT_3_CONFIGURATION
0x422R1058OUT_3_CHAN_POL_SELOUT_3_CLK_MUXRESERVEDOUT_3_DIV_ENOUT_3_CH_MUX_SEL
0x423R1059RESERVEDOUT_3_MUTE_ENOUT_3_SYNC_ENRESERVED
0x424R1060RESERVEDOUT_3_CH_STATIC_OFFSET_11:8
0x425R1061OUT_3_CH_STATIC_OFFSET
0x426R1062RESERVEDOUT_3_CH_DIV_11:8
0x427R1063OUT_3_CH_DIV
0x440R1088RESERVEDOUT_4_5_SR_ANA_DLY_BIASTRIM
0x441R1089RESERVEDOUT_4_ENOUT_4_FMT
0x442R1090RESERVEDOUT_4_CAP_ENRESERVEDOUT_4_CONFIGURATION
0x443R1091RESERVEDOUT_5_ENOUT_5_FMT
0x444R1092RESERVEDOUT_5_CAP_ENRESERVEDOUT_5_CONFIGURATION
0x445R1093RESERVEDOUT_4_5_DIV_SYNC_ENOUT_4_5_SR_DIV_SYNC_ENRESERVEDOUT_4_5_CHAN_POL_SELOUT_4_5_DIV_EN
0x446R1094OUT_4_5_MUTE_ENOUT_4_5_ZDM_ENOUT_4_5_CLK_IN_SELOUT_4_5_CH_DIV_SR_MUX_CLK_SELOUT_4_5_CH_MUX_SEL
0x447R1095RESERVEDOUT_4_5_CH_STATIC_OFFSET_11:8
0x448R1096OUT_4_5_CH_STATIC_OFFSET
0x449R1097RESERVEDOUT_4_5_CH_DIV_11:8
0x44AR1098OUT_4_5_CH_DIV
0x44BR1099RESERVEDOUT_4_5_SR_ANA_DELAY
0x44CR1100RESERVEDOUT_4_5_SR_ANA_DELAY_DIV2_SELOUT_4_5_SR_ANA_DELAY_ENOUT_4_5_SR_ANA_DELAY_SMALL_STEP_ENOUT_4_5_SR_ANA_DELAY_RANGE
0x44DR1101RESERVEDOUT_4_5_SR_DDLY
0x44ER1102RESERVEDOUT_4_5_SR_DIV_19:16
0x44FR1103OUT_4_5_SR_DIV_15:8
0x450R1104OUT_4_5_SR_DIV
0x451R1105RESERVEDOUT_4_5_SR_DIV_STATIC_OFFSET_14:8
0x452R1106OUT_4_5_SR_DIV_STATIC_OFFSET
0x453R1107RESERVEDOUT_4_5_SR_REQ_MODEOUT_4_5_PULSE_COUNTOUT_4_5_SR_GPIO_ENOUT_4_5_SR_MODE
0x454R1108RESERVEDOUT_4_5_SR_CH_DIV_BYPASSRESERVED
0x461R1121RESERVEDOUT_6_ENOUT_6_FMT
0x462R1122RESERVEDOUT_6_CAP_ENRESERVEDOUT_6_CONFIGURATION
0x463R1123RESERVEDOUT_7_ENOUT_7_FMT
0x464R1124RESERVEDOUT_7_CAP_ENRESERVEDOUT_7_CONFIGURATION
0x465R1125RESERVEDOUT_6_7_DIV_SYNC_ENOUT_6_7_SR_DIV_SYNC_ENRESERVEDOUT_6_7_CHAN_POL_SELOUT_6_7_DIV_EN
0x466R1126OUT_6_7_MUTE_ENRESERVEDOUT_6_7_CLK_IN_SELOUT_6_7_CH_DIV_SR_MUX_CLK_SELOUT_6_7_CH_MUX_SEL
0x467R1127RESERVEDOUT_6_7_CH_STATIC_OFFSET_11:8
0x468R1128OUT_6_7_CH_STATIC_OFFSET
0x469R1129RESERVEDOUT_6_7_CH_DIV_11:8
0x46AR1130OUT_6_7_CH_DIV
0x46BR1131RESERVEDOUT_6_7_SR_ANA_DELAY
0x46CR1132RESERVEDOUT_6_7_SR_ANA_DELAY_DIV2_SELOUT_6_7_SR_ANA_DELAY_ENOUT_6_7_SR_ANA_DELAY_SMALL_STEP_ENOUT_6_7_SR_ANA_DELAY_RANGE
0x46DR1133RESERVEDOUT_6_7_SR_DDLY
0x46ER1134RESERVEDOUT_6_7_SR_DIV_19:16
0x46FR1135OUT_6_7_SR_DIV_15:8
0x470R1136OUT_6_7_SR_DIV
0x471R1137RESERVEDOUT_6_7_SR_DIV_STATIC_OFFSET_14:8
0x472R1138OUT_6_7_SR_DIV_STATIC_OFFSET
0x473R1139RESERVEDOUT_6_7_SR_REQ_MODEOUT_6_7_PULSE_COUNTOUT_6_7_SR_GPIO_ENOUT_6_7_SR_MODE
0x474R1140RESERVEDOUT_6_7_SR_CH_DIV_BYPASSRESERVED
0x481R1153RESERVEDOUT_8_ENOUT_8_FMT
0x482R1154RESERVEDOUT_8_CAP_ENRESERVEDOUT_8_CONFIGURATION
0x483R1155RESERVEDOUT_9_ENOUT_9_FMT
0x484R1156RESERVEDOUT_9_CAP_ENRESERVEDOUT_9_CONFIGURATION
0x485R1157RESERVEDOUT_8_9_DIV_SYNC_ENOUT_8_9_SR_DIV_SYNC_ENRESERVEDOUT_8_9_CHAN_POL_SELOUT_8_9_DIV_EN
0x486R1158OUT_8_9_MUTE_ENRESERVEDOUT_8_9_CLK_IN_SELOUT_8_9_CH_DIV_SR_MUX_CLK_SELOUT_8_9_CH_MUX_SEL
0x487R1159RESERVEDOUT_8_9_CH_STATIC_OFFSET_11:8
0x488R1160OUT_8_9_CH_STATIC_OFFSET
0x489R1161RESERVEDOUT_8_9_CH_DIV_11:8
0x48AR1162OUT_8_9_CH_DIV
0x48BR1163RESERVEDOUT_8_9_SR_ANA_DELAY
0x48CR1164RESERVEDOUT_8_9_SR_ANA_DELAY_DIV2_SELOUT_8_9_SR_ANA_DELAY_ENOUT_8_9_SR_ANA_DELAY_SMALL_STEP_ENOUT_8_9_SR_ANA_DELAY_RANGE
0x48DR1165RESERVEDOUT_8_9_SR_DDLY
0x48ER1166RESERVEDOUT_8_9_SR_DIV_19:16
0x48FR1167OUT_8_9_SR_DIV_15:8
0x490R1168OUT_8_9_SR_DIV
0x491R1169RESERVEDOUT_8_9_SR_DIV_STATIC_OFFSET_14:8
0x492R1170OUT_8_9_SR_DIV_STATIC_OFFSET
0x493R1171RESERVEDOUT_8_9_SR_REQ_MODEOUT_8_9_PULSE_COUNTOUT_8_9_SR_GPIO_ENOUT_8_9_SR_MODE
0x4A1R1185RESERVEDOUT_10_ENOUT_10_FMT
0x4A2R1186RESERVEDOUT_10_CAP_ENRESERVEDOUT_10_CONFIGURATION
0x4A3R1187RESERVEDOUT_11_ENOUT_11_FMT
0x4A4R1188RESERVEDOUT_11_CAP_ENRESERVEDOUT_11_CONFIGURATION
0x4A5R1189RESERVEDOUT_10_11_DIV_SYNC_ENOUT_10_11_SR_DIV_SYNC_ENRESERVEDOUT_10_11_CHAN_POL_SELOUT_10_11_DIV_EN
0x4A6R1190OUT_10_11_MUTE_ENOUT_10_11_ZDM_ENOUT_10_11_CLK_IN_SELOUT_10_11_CH_DIV_SR_MUX_CLK_SELOUT_10_11_CH_MUX_SEL
0x4A7R1191RESERVEDOUT_10_11_CH_STATIC_OFFSET_11:8
0x4A8R1192OUT_10_11_CH_STATIC_OFFSET
0x4A9R1193RESERVEDOUT_10_11_CH_DIV_11:8
0x4AAR1194OUT_10_11_CH_DIV
0x4ABR1195RESERVEDOUT_10_11_SR_ANA_DELAY
0x4ACR1196RESERVEDOUT_10_11_SR_ANA_DELAY_DIV2_SELOUT_10_11_SR_ANA_DELAY_ENOUT_10_11_SR_ANA_DELAY_SMALL_STEP_ENOUT_10_11_SR_ANA_DELAY_RANGE
0x4ADR1197RESERVEDOUT_10_11_SR_DDLY
0x4AER1198RESERVEDOUT_10_11_SR_DIV_19:16
0x4AFR1199OUT_10_11_SR_DIV_15:8
0x4B0R1200OUT_10_11_SR_DIV
0x4B1R1201RESERVEDOUT_10_11_SR_DIV_STATIC_OFFSET_14:8
0x4B2R1202OUT_10_11_SR_DIV_STATIC_OFFSET
0x4B3R1203RESERVEDOUT_10_11_SR_REQ_MODEOUT_10_11_PULSE_COUNTOUT_10_11_SR_GPIO_ENOUT_10_11_SR_MODE
0x4B4R1204RESERVEDOUT_10_11_SR_CH_DIV_BYPASSRESERVED
0x4C1R1217RESERVEDOUT_12_ENOUT_12_FMT
0x4C2R1218RESERVEDOUT_12_CAP_ENRESERVEDOUT_12_CONFIGURATION
0x4C3R1219RESERVEDOUT_13_ENOUT_13_FMT
0x4C4R1220RESERVEDOUT_13_CAP_ENRESERVEDOUT_13_CONFIGURATION
0x4C5R1221RESERVEDOUT_12_13_DIV_SYNC_ENOUT_12_13_SR_DIV_SYNC_ENRESERVEDOUT_12_13_CHAN_POL_SELOUT_12_13_DIV_EN
0x4C6R1222OUT_12_13_MUTE_ENRESERVEDOUT_12_13_CLK_IN_SELOUT_12_13_CH_DIV_SR_MUX_CLK_SELOUT_12_13_CH_MUX_SEL
0x4C7R1223RESERVEDOUT_12_13_CH_STATIC_OFFSET_11:8
0x4C8R1224OUT_12_13_CH_STATIC_OFFSET
0x4C9R1225RESERVEDOUT_12_13_CH_DIV_11:8
0x4CAR1226OUT_12_13_CH_DIV
0x4CBR1227RESERVEDOUT_12_13_SR_ANA_DELAY
0x4CCR1228RESERVEDOUT_12_13_SR_ANA_DELAY_DIV2_SELOUT_12_13_SR_ANA_DELAY_ENOUT_12_13_SR_ANA_DELAY_SMALL_STEP_ENOUT_12_13_SR_ANA_DELAY_RANGE
0x4CDR1229RESERVEDOUT_12_13_SR_DDLY
0x4CER1230RESERVEDOUT_12_13_SR_DIV_19:16
0x4CFR1231OUT_12_13_SR_DIV_15:8
0x4D0R1232OUT_12_13_SR_DIV
0x4D1R1233RESERVEDOUT_12_13_SR_DIV_STATIC_OFFSET_14:8
0x4D2R1234OUT_12_13_SR_DIV_STATIC_OFFSET
0x4D3R1235RESERVEDOUT_12_13_SR_REQ_MODEOUT_12_13_PULSE_COUNTOUT_12_13_SR_GPIO_ENOUT_12_13_SR_MODE
0x4D4R1236RESERVEDOUT_12_13_SR_CH_DIV_BYPASSRESERVED
0x4E0R1248RESERVEDOUT_14_FMT
0x500R1280RESERVEDOUT_15_FMT

Complex bit access types are encoded to fit into small table cells. Table 1-2 shows the codes that are used for access types in this section.

Table 1-2 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1SW
1S		Write
1 to set
WSCWWrite
Reset or Default Value
-nValue after reset or the default value

1.1 R0 (Offset = 0x0)

Return to the Summary Table.

Table 1-3 R0 Field Descriptions
BitFieldTypeResetDescription
7:0VNDRID_15:8R0x0 See Register 1

1.2 R1 (Offset = 0x1)

Return to the Summary Table.

Table 1-4 R1 Field Descriptions
BitFieldTypeResetDescription
7:0VNDRIDR0x0 Vendor Identification Number. The Vendor Identification Number is a unique 16-bit identification number assigned to I2C/SMBus vendors.
ROM=N, EEPROM=N

1.3 R2 (Offset = 0x2)

Return to the Summary Table.

Table 1-5 R2 Field Descriptions
BitFieldTypeResetDescription
7:0PRODIDR0x0 Product ID.
ROM=N, EEPROM=N

1.4 R3 (Offset = 0x3)

Return to the Summary Table.

Table 1-6 R3 Field Descriptions
BitFieldTypeResetDescription
7:0REVIDR0x1 Revision ID.
ROM=N, EEPROM=N

1.5 R4 (Offset = 0x4)

Return to the Summary Table.

Table 1-7 R4 Field Descriptions
BitFieldTypeResetDescription
7:0PRTID_47:40R0x5A Part ID. Used for manufacturing
ROM=N, EEPROM=Y

1.6 R5 (Offset = 0x5)

Return to the Summary Table.

Table 1-8 R5 Field Descriptions
BitFieldTypeResetDescription
7:0PRTID_39:32R0xE4 Part ID. Used for manufacturing
ROM=N, EEPROM=Y

1.7 R6 (Offset = 0x6)

Return to the Summary Table.

Table 1-9 R6 Field Descriptions
BitFieldTypeResetDescription
7:0PRTID_31:24R0x1B Part ID. Used for manufacturing
ROM=N, EEPROM=Y

1.8 R7 (Offset = 0x7)

Return to the Summary Table.

Table 1-10 R7 Field Descriptions
BitFieldTypeResetDescription
7:0PRTID_23:16R0x80 Part ID. Used for manufacturing
ROM=N, EEPROM=Y

1.9 R8 (Offset = 0x8)

Return to the Summary Table.

Table 1-11 R8 Field Descriptions
BitFieldTypeResetDescription
7:0PRTID_15:8R0x1 Part ID. Used for manufacturing
ROM=N, EEPROM=Y

1.10 R9 (Offset = 0x9)

Return to the Summary Table.

Table 1-12 R9 Field Descriptions
BitFieldTypeResetDescription
7:0PRTIDR0x81 Part ID. Used for manufacturing
ROM=N, EEPROM=Y

1.11 R16 (Offset = 0x10)

Return to the Summary Table.

Table 1-13 R16 Field Descriptions
BitFieldTypeResetDescription
7:0NVMCNTR0x0 NVM Program Count. The NVMCNT increments automatically after every EEPROM Erase/Program Cycle. The NVMCNT value is retrieved automatically after reset, after a NVM Commit operation, or after a Erase/Program cycle. The NVMCNT register will increment until it reaches it's maximum value of 255 after which no further increments will take place.
ROM=N, EEPROM=Y

1.12 R18 (Offset = 0x12)

Return to the Summary Table.

Table 1-14 R18 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0TARGET_ADR_MSBR0x19 I2C/SMBus Target Address. This field holds the 5 MSB bits of the Target Address used to identify this device during I2C/SMBus transactions. The two least significant bits of the Target Address are defined by CSC/ADD/TEC pin upon power-up. This is user-writable to EEPROM only through SRAM register at address 12.
ROM=N, EEPROM=Y

1.13 R19 (Offset = 0x13)

Return to the Summary Table.

Table 1-15 R19 Field Descriptions
BitFieldTypeResetDescription
7:0EEREVR/W0x0 EEPROM Image Revision ID. EEPROM Image Revision is automatically retrieved from EEPROM and stored in the EEREV register after a reset or after a NVM commit operation. This is user-writable to EEPROM only through SRAM register address 13.
ROM=N, EEPROM=Y

1.14 R20 (Offset = 0x14)

Return to the Summary Table.

Table 1-16 R20 Field Descriptions
BitFieldTypeResetDescription
7ROM_PLUS_EER/W0x0 When set, the thin EEPROM settings are loaded. This is user-writable to EEPROM only through SRAM register address 14.
ROM=N, EEPROM=Y
6:3EE_ROM_PAGE_SELR/W0x0 EE_ROM_PAGE_SEL value is added to the GPIO pin value for selecting the start-up ROM.
ROM=N, EEPROM=Y
2:0RESERVEDR0x0 Reserved

1.15 R21 (Offset = 0x15)

Return to the Summary Table.

Table 1-17 R21 Field Descriptions
BitFieldTypeResetDescription
7SPI_3WIRE_DISR/W0x0 Disable SPI 3 wire readback. The SDIO pin will remain input at all times.
ROM=Y, EEPROM=N
  • 0x0 = 3-wire SPI readback enabled
  • 0x1 = 3-wire SPI readback disabled
6SYNC_SWR/W0x0 Software SYNC Assertion. Writing a '1' to this bit is equivalent to asserting the SYNC pin. SYNC_EN must also be set to 1.
ROM=Y, EEPROM=Y
5:0RESERVEDR0x0 Reserved

1.16 R22 (Offset = 0x16)

Return to the Summary Table.

Table 1-18 R22 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5DPLL3_ENR/W0x0 Enable DPLL3.
ROM=Y, EEPROM=N
4APLL3_ENR/W0x1 Enable APLL3.
ROM=Y, EEPROM=Y
3DPLL2_ENR/W0x0 Enable DPLL2.
ROM=Y, EEPROM=N
2APLL2_ENR/W0x1 Enable APLL2.
ROM=Y, EEPROM=Y
1DPLL1_ENR/W0x0 Enable DPLL1.
ROM=Y, EEPROM=N
0APLL1_ENR/W0x1 Enable APLL1.
ROM=Y, EEPROM=Y

1.17 R23 (Offset = 0x17)

Return to the Summary Table.

Table 1-19 R23 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6SWRSTR/W0x0 Software Reset ALL functions (active low). Writing a '0' will cause the device to return to its power-up state apart from the programmed registers and the configuration controller. The configuration controller is excluded to prevent an re-transfer of EEPROM data to on-chip registers. Not a self clearing field.
ROM=N, EEPROM=N
5:0RESERVEDR0x0 Reserved

1.18 R24 (Offset = 0x18)

Return to the Summary Table.

Table 1-20 R24 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:4APLL3_STRT_PRTYR/W0x1 APLL3 Start-up Priority. 0 is highest priority. APLLs with the same priority will start simultaneously.
ROM=Y, EEPROM=Y
3:2APLL2_STRT_PRTYR/W0x2 APLL2 Start-up Priority. 0 is highest priority. APLLs with the same priority will start simultaneously.
ROM=Y, EEPROM=Y
1:0APLL1_STRT_PRTYR/W0x2 APLL1 Start-up Priority. 0 is highest priority. APLLs with the same priority will start simultaneously.
ROM=Y, EEPROM=Y

1.19 R25 (Offset = 0x19)

Return to the Summary Table.

Table 1-21 R25 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:1RESERVEDR0x0 Reserved
0SYNC_ENR/W0x0 Allows SYNC from SYNC_SW and GPIO pin. For GPIO sync, must be set together with SYNC input for GPIOx_MODE.
ROM=Y, EEPROM=Y

1.20 R26 (Offset = 0x1A)

Return to the Summary Table.

Table 1-22 R26 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:4SYSREF_REQ_MODER/W0x0 SYSREF Request Mode. Determines how a GPIO input is syncronized to generate a SYSREF request.
ROM=Y, EEPROM=N
  • 0x0 = Direct SYSREF request
  • 0x1 = Reserved
  • 0x2 = Reserved
  • 0x3 = Resampled SYSREF request
3:1SYSREF_REQ_SELR/W0x0 SYSREF Request Select. Choses which output drives the SYSREF feedback clock.
ROM=Y, EEPROM=N
  • 0x0 = SYSREF0_1_CLK
  • 0x1 = SYSREF4_5_CLK
  • 0x2 = SYSREF6_7_CLK
  • 0x3 = SYSREF8_9_CLK
  • 0x4 = SYSREF10_11_CLK
  • 0x5 = SYSREF12_13_CLK
  • 0x6 = Reserved
0SYSREF_REQ_SWR/WSC0x0 Software SYSREF request trigger
ROM=N, EEPROM=N

1.21 R27 (Offset = 0x1B)

Return to the Summary Table.

Table 1-23 R27 Field Descriptions
BitFieldTypeResetDescription
7:0TEC_CNTR_39:32R0x0 Time Elapsed Counter Readback
ROM=N, EEPROM=N

1.22 R28 (Offset = 0x1C)

Return to the Summary Table.

Table 1-24 R28 Field Descriptions
BitFieldTypeResetDescription
7:0TEC_CNTR_31:24R0x0 Time Elapsed Counter Readback
ROM=N, EEPROM=N

1.23 R29 (Offset = 0x1D)

Return to the Summary Table.

Table 1-25 R29 Field Descriptions
BitFieldTypeResetDescription
7:0TEC_CNTR_23:16R0x0 Time Elapsed Counter Readback
ROM=N, EEPROM=N

1.24 R30 (Offset = 0x1E)

Return to the Summary Table.

Table 1-26 R30 Field Descriptions
BitFieldTypeResetDescription
7:0TEC_CNTR_15:8R0x0 Time Elapsed Counter Readback
ROM=N, EEPROM=N

1.25 R31 (Offset = 0x1F)

Return to the Summary Table.

Table 1-27 R31 Field Descriptions
BitFieldTypeResetDescription
7:0TEC_CNTRR0x0 Time Elapsed Counter Readback
ROM=N, EEPROM=N

1.26 R32 (Offset = 0x20)

Return to the Summary Table.

Table 1-28 R32 Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0x0 Reserved
2RESERVEDR0x0 Reserved
1TEC_CNTR_TRIG_SELR/W0x0 Time Elapsed Counter trigger select. If using GPIO, must also set GPIOx_MODE to provide TEC trigger.
ROM=Y, EEPROM=N
  • 0x0 = SPI
  • 0x1 = GPIO
0TEC_CNTR_ENR/W0x0 Time Elapsed Counter counter enable. When transitioning from 0 --> 1, the TEC counter will start from 0.
ROM=Y, EEPROM=N

1.27 R33 (Offset = 0x21)

Return to the Summary Table.

Table 1-29 R33 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3LOL_PLL1R0x0 Loss of Lock - APLL1
ROM=N, EEPROM=N
2LOL_PLL2R0x0 Loss of Lock - APLL2
ROM=N, EEPROM=N
1RESERVEDR0x0 Reserved
0LOS_FDET_XOR0x0 Loss of Source Freq Detection - XO
ROM=N, EEPROM=N

1.28 R34 (Offset = 0x22)

Return to the Summary Table.

Table 1-30 R34 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL1R0x0 Loss of Phase Lock - DPLL1
ROM=N, EEPROM=N
6LOFL_DPLL1R0x0 Loss of Frequency Lock - DPLL1
ROM=N, EEPROM=N
5RESERVEDR0x0 Reserved
4HLDOVR1R0x0 Holdover event - DPLL1
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.29 R35 (Offset = 0x23)

Return to the Summary Table.

Table 1-31 R35 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL2R0x0 Loss of Phase Lock - DPLL2
ROM=N, EEPROM=N
6LOFL_DPLL2R0x0 Loss of Frequency Lock - DPLL2
ROM=N, EEPROM=N
5RESERVEDR0x0 Reserved
4HLDOVR2R0x0 Holdover event - DPLL2
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.30 R36 (Offset = 0x24)

Return to the Summary Table.

Table 1-32 R36 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL3R0x0 Loss of Phase Lock - DPLL3
ROM=N, EEPROM=N
6LOFL_DPLL3R0x0 Loss of Frequency Lock - DPLL3
ROM=N, EEPROM=N
5RESERVEDR0x0 Reserved
4HLDOVR3R0x0 Holdover event - DPLL3
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.31 R37 (Offset = 0x25)

Return to the Summary Table.

Table 1-33 R37 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3LOL_PLL1_MASKR/W0x0 Masks Loss of Lock - APLL1. When LOL_PLL1_MASK is 1 then the LOL_PLL1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
2LOL_PLL2_MASKR/W0x0 Masks Loss of Lock - APLL2. When LOL_PLL2_MASK is 1 then the LOL_PLL2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
1RESERVEDR0x0 Reserved
0LOS_FDET_XO_MASKR/W0x0 Masks Loss of Source Freq Detection - XO. When LOS_FDET_XO_MASK is 1 then the LOS_FDET_XO interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N

1.32 R38 (Offset = 0x26)

Return to the Summary Table.

Table 1-34 R38 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL1_MASKR/W0x0 Masks Loss of Phase Lock - DPLL1. When LOPL_DPLL1_MASK is 1 then the LOPL_DPLL1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
6LOFL_DPLL1_MASKR/W0x0 Masks Loss of Freq Lock - DPLL1. When LOFL_DPLL1_MASK is 1 then the LOFL_DPLL1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
5HIST1_MASKR/W0x0 Masks Tuning word history update - DPLL1. When HIST1_MASK is 1 then the HIST1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
4HLDOVR1_MASKR/W0x0 Masks Holdover event - DPLL1. When HLDOVR1_MASK is 1 then the HLDOVR1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
3REFSWITCH1_MASKR/W0x0 Masks Reference Switchover - DPLL1. When REFSWITCH1_MASK is 1 then the REFSWITCH1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
2LOR_MISSCLK1_MASKR/W0x0 Masks Loss of Active Reference - Missing Clock - DPLL1. When LOR_MISSCLK1_MASK is 1 then the LOR_MISSCLK1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
1LOR_FREQ1_MASKR/W0x0 Masks Loss of Active Reference - Frequency - DPLL1. When LOR_FREQ1_MASK is 1 then the LOR_FREQ1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
0LOR_PH1_MASKR/W0x0 Masks Loss of Active Reference - Phase - DPLL1. When LOR_PH1_MASK is 1 then the LOR_PH1 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N

1.33 R39 (Offset = 0x27)

Return to the Summary Table.

Table 1-35 R39 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL2_MASKR/W0x0 Masks Loss of Phase Lock - DPLL2. When LOPL_DPLL2_MASK is 1 then the LOPL_DPLL2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
6LOFL_DPLL2_MASKR/W0x0 Masks Loss of Freq Lock - DPLL2. When LOFL_DPLL2_MASK is 1 then the LOFL_DPLL2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
5HIST2_MASKR/W0x0 Masks Tuning word history update - DPLL2. When HIST2_MASK is 1 then the HIST2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
4HLDOVR2_MASKR/W0x0 Masks Holdover event - DPLL2. When HLDOVR2_MASK is 1 then the HLDOVR2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
3REFSWITCH2_MASKR/W0x0 Masks Reference Switchover - DPLL2. When REFSWITCH2_MASK is 1 then the REFSWITCH2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
2LOR_MISSCLK2_MASKR/W0x0 Masks Loss of Active Reference - Missing Clock - DPLL2. When LOR_MISSCLK2_MASK is 1 then the LOR_MISSCLK2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
1LOR_FREQ2_MASKR/W0x0 Masks Loss of Active Reference - Frequency - DPLL2. When LOR_FREQ2_MASK is 1 then the LOR_FREQ2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
0LOR_PH2_MASKR/W0x0 Masks Loss of Active Reference - Phase - DPLL2. When LOR_PH2_MASK is 1 then the LOR_PH2 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N

1.34 R40 (Offset = 0x28)

Return to the Summary Table.

Table 1-36 R40 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL3_MASKR/W0x0 Masks Loss of Phase Lock - DPLL3. When LOPL_DPLL3_MASK is 1 then the LOPL_DPLL3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
6LOFL_DPLL3_MASKR/W0x0 Masks Loss of Freq Lock - DPLL3. When LOFL_DPLL3_MASK is 1 then the LOFL_DPLL3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
5HIST3_MASKR/W0x0 Masks Tuning word history update - DPLL3. When HIST3_MASK is 1 then the HIST3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
4HLDOVR3_MASKR/W0x0 Masks Holdover event - DPLL3. When HLDOVR3_MASK is 1 then the HLDOVR3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
3REFSWITCH3_MASKR/W0x0 Masks Reference Switchover - DPLL3. When REFSWITCH3_MASK is 1 then the REFSWITCH3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
2LOR_MISSCLK3_MASKR/W0x0 Masks Loss of Active Reference - Missing Clock - DPLL3. When LOR_MISSCLK3_MASK is 1 then the LOR_MISSCLK3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
1LOR_FREQ3_MASKR/W0x0 Masks Loss of Active Reference - Frequency - DPLL3. When LOR_FREQ3_MASK is 1 then the LOR_FREQ3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N
0LOR_PH3_MASKR/W0x0 Masks Loss of Active Reference - Phase - DPLL3. When LOR_PH3_MASK is 1 then the LOR_PH3 interrupt source is masked and will not cause the interrupt signal to be activated.
ROM=Y, EEPROM=N

1.35 R41 (Offset = 0x29)

Return to the Summary Table.

Table 1-37 R41 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3LOL_PLL1_POLR/W0x0 LOL_PLL1 Flag Polarity. When LOL_PLL1_POL = 1,LOL_PLL1 = 0 results in LOL_PLL1_INTR = 1. When LOL_PLL1_POL = 0, LOL_PLL1 = 1 results in LOL_PLL1_INTR = 1.
ROM=Y, EEPROM=N
2LOL_PLL2_POLR/W0x0 LOL_PLL2 Flag Polarity. When LOL_PLL2_POL = 1,LOL_PLL2 = 0 results in LOL_PLL2_INTR = 1. When LOL_PLL2_POL = 0, LOL_PLL2 = 1 results in LOL_PLL2_INTR = 1.
ROM=Y, EEPROM=N
1RESERVEDR0x0 Reserved
0LOS_FDET_XO_POLR/W0x0 LOS_FDET_XO Flag Polarity. When LOS_FDET_XO_POL = 1, LOS_FDET_XO = 0 results in LOS_FDET_XO_INTR = 1. When LOS_FDET_XO_POL = 0, LOS_FDET_XO = 1 results in LOS_FDET_XO_INTR = 1.
ROM=Y, EEPROM=N

1.36 R42 (Offset = 0x2A)

Return to the Summary Table.

Table 1-38 R42 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL1_POLR/W0x0 LOPL_DPLL1 Flag Polarity. When LOPL_DPLL1_POL = 1, LOPL_DPLL1 = 0 results in LOPL_DPLL1_INTR = 1. When LOPL_DPLL1_POL = 0, LOPL_DPLL1 = 1 results in LOPL_DPLL1_INTR = 1.
ROM=Y, EEPROM=N
6LOFL_DPLL1_POLR/W0x0 LOFL_DPLL1 Flag Polarity. When LOFL_DPLL1_POL = 1, LOFL_DPLL1 = 0 results in LOFL_DPLL1_INTR = 1. When LOFL_DPLL1_POL = 0, LOFL_DPLL1 = 1 results in LOFL_DPLL1_INTR = 1.
ROM=Y, EEPROM=N
5HIST1_POLR/W0x0 HIST1 Flag Polarity. When HIST1_POL = 1, HIST1 = 0 results in HIST1_INTR = 1. When HIST1_POL = 0, HIST1 = 1 results in HIST1_INTR = 1.
ROM=Y, EEPROM=N
4HLDOVR1_POLR/W0x0 HLDOVR1 Flag Polarity. When HLDOVR1_POL = 1, HLDOVR1 = 0 results in HLDOVR1_INTR = 1. When HLDOVR1_POL = 0, HLDOVR1 = 1 results in HLDOVR1_INTR = 1.
ROM=Y, EEPROM=N
3REFSWITCH1_POLR/W0x0 REFSWITCH1 Flag Polarity. When REFSWITCH1_POL = 1, REFSWITCH1 = 0 results in REFSWITCH1_INTR = 1. When REFSWITCH1_POL = 0, REFSWITCH1 = 1 results in REFSWITCH1_INTR = 1.
ROM=Y, EEPROM=N
2LOR_MISSCLK1_POLR/W0x0 LOR_MISSCLK1 Flag Polarity. When LOR_MISSCLK1_POL = 1, LOR_MISSCLK1 = 0 results in LOR_MISSCLK1_INTR = 1. When LOR_MISSCLK1_POL = 0, LOR_MISSCLK1 = 1 results in LOR_MISSCLK1_INTR = 1.
ROM=Y, EEPROM=N
1LOR_FREQ1_POLR/W0x0 LOR_FREQ1 Flag Polarity. When LOR_FREQ1_POL = 1, LOR_FREQ1 = 0 results in LOR_FREQ1_INTR = 1. When LOR_FREQ1_POL = 0, LOR_FREQ1 = 1 results in LOR_FREQ1_INTR = 1.
ROM=Y, EEPROM=N
0LOR_PH1_POLR/W0x0 LOR_PH1 Flag Polarity. When LOR_PH1_POL = 1, LOR_PH1 = 0 results in LOR_PH1_INTR = 1. When LOR_PH1_POL = 0, LOR_PH1 = 1 results in LOR_PH1_INTR = 1.
ROM=Y, EEPROM=N

1.37 R43 (Offset = 0x2B)

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Table 1-39 R43 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL2_POLR/W0x0 LOPL_DPLL2 Flag Polarity. When LOPL_DPLL2_POL = 1, LOPL_DPLL2 = 0 results in LOPL_DPLL2_INTR = 1. When LOPL_DPLL2_POL = 0, LOPL_DPLL2 = 1 results in LOPL_DPLL2_INTR = 1.
ROM=Y, EEPROM=N
6LOFL_DPLL2_POLR/W0x0 LOFL_DPLL2 Flag Polarity. When LOFL_DPLL2_POL = 1, LOFL_DPLL2 = 0 results in LOFL_DPLL2_INTR = 1. When LOFL_DPLL2_POL = 0, LOFL_DPLL2 = 1 results in LOFL_DPLL2_INTR = 1.
ROM=Y, EEPROM=N
5HIST2_POLR/W0x0 HIST2 Flag Polarity. When HIST2_POL = 1, HIST2 = 0 results in HIST2_INTR = 1. When HIST2_POL = 0, HIST2 = 1 results in HIST2_INTR = 1.
ROM=Y, EEPROM=N
4HLDOVR2_POLR/W0x0 HLDOVR2 Flag Polarity. When HLDOVR2_POL = 1, HLDOVR2 = 0 results in HLDOVR2_INTR = 1. When HLDOVR2_POL = 0, HLDOVR2 = 1 results in HLDOVR2_INTR = 1.
ROM=Y, EEPROM=N
3REFSWITCH2_POLR/W0x0 REFSWITCH2 Flag Polarity. When REFSWITCH2_POL = 1, REFSWITCH2 = 0 results in REFSWITCH2_INTR = 1. When REFSWITCH2_POL = 0, REFSWITCH2 = 1 results in REFSWITCH2_INTR = 1.
ROM=Y, EEPROM=N
2LOR_MISSCLK2_POLR/W0x0 LOR_MISSCLK2 Flag Polarity. When LOR_MISSCLK2_POL = 1, LOR_MISSCLK2 = 0 results in LOR_MISSCLK2_INTR = 1. When LOR_MISSCLK2_POL = 0, LOR_MISSCLK2 = 1 results in LOR_MISSCLK2_INTR = 1.
ROM=Y, EEPROM=N
1LOR_FREQ2_POLR/W0x0 LOR_FREQ2 Flag Polarity. When LOR_FREQ2_POL = 1, LOR_FREQ2 = 0 results in LOR_FREQ2_INTR = 1. When LOR_FREQ2_POL = 0, LOR_FREQ2 = 1 results in LOR_FREQ2_INTR = 1.
ROM=Y, EEPROM=N
0LOR_PH2_POLR/W0x0 LOR_PH2 Flag Polarity. When LOR_PH2_POL = 1, LOR_PH2 = 0 results in LOR_PH2_INTR = 1. When LOR_PH2_POL = 0, LOR_PH2 = 1 results in LOR_PH2_INTR = 1.
ROM=Y, EEPROM=N

1.38 R44 (Offset = 0x2C)

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Table 1-40 R44 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL3_POLR/W0x0 LOPL_DPLL3 Flag Polarity. When LOPL_DPLL3_POL = 1, LOPL_DPLL3 = 0 results in LOPL_DPLL3_INTR = 1. When LOPL_DPLL3_POL = 0, LOPL_DPLL3 = 1 results in LOPL_DPLL3_INTR = 1.
ROM=Y, EEPROM=N
6LOFL_DPLL3_POLR/W0x0 LOFL_DPLL3 Flag Polarity. When LOFL_DPLL3_POL = 1, LOFL_DPLL3 = 0 results in LOFL_DPLL3_INTR = 1. When LOFL_DPLL3_POL = 0, LOFL_DPLL3 = 1 results in LOFL_DPLL3_INTR = 1.
ROM=Y, EEPROM=N
5HIST3_POLR/W0x0 HIST3 Flag Polarity. When HIST3_POL = 1, HIST3 = 0 results in HIST3_INTR = 1. When HIST3_POL = 0, HIST3 = 1 results in HIST3_INTR = 1
ROM=Y, EEPROM=N
4HLDOVR3_POLR/W0x0 HLDOVR3 Flag Polarity. When HLDOVR3_POL = 1, HLDOVR3 = 0 results in HLDOVR3_INTR = 1. When HLDOVR3_POL = 0, HLDOVR3 = 1 results in HLDOVR3_INTR = 1.
ROM=Y, EEPROM=N
3REFSWITCH3_POLR/W0x0 REFSWITCH3 Flag Polarity. When REFSWITCH3_POL = 1, REFSWITCH3 = 0 results in REFSWITCH3_INTR = 1. When REFSWITCH3_POL = 0, REFSWITCH3 = 1 results in REFSWITCH3_INTR = 1.
ROM=Y, EEPROM=N
2LOR_MISSCLK3_POLR/W0x0 LOR_MISSCLK3 Flag Polarity. When LOR_MISSCLK3_POL = 1, LOR_MISSCLK3 = 0 results in LOR_MISSCLK3_INTR = 1. When LOR_MISSCLK3_POL = 0, LOR_MISSCLK3 = 1 results in LOR_MISSCLK3_INTR = 1.
ROM=Y, EEPROM=N
1LOR_FREQ3_POLR/W0x0 LOR_FREQ3 Flag Polarity. When LOR_FREQ3_POL = 1, LOR_FREQ3 = 0 results in LOR_FREQ3_INTR = 1. When LOR_FREQ3_POL = 0, LOR_FREQ3 = 1 results in LOR_FREQ3_INTR = 1.
ROM=Y, EEPROM=N
0LOR_PH3_POLR/W0x0 LOR_PH3 Flag Polarity. When LOR_PH3_POL = 1, LOR_PH3 = 0 results in LOR_PH3_INTR = 1. When LOR_PH3_POL = 0, LOR_PH3 = 1 results in LOR_PH3_INTR = 1.
ROM=Y, EEPROM=N

1.39 R45 (Offset = 0x2D)

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Table 1-41 R45 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3LOL_PLL1_INTRR0x0 LOL_PLL1 Interrupt. The LOL_PLL1_INTR bit is set when a level of the correct polarity is detected on the LOL_PLL1 interrupt source. The LOL_PLL1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
2LOL_PLL2_INTRR0x0 LOL_PLL2 Interrupt. The LOL_PLL2_INTR bit is set when a level of the correct polarity is detected on the LOL_PLL2 interrupt source. The LOL_PLL2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
1RESERVEDR0x0 Reserved
0LOS_FDET_XO_INTRR0x0 LOL_FDET_XO Interrupt. The LOL_FDET_XO_INTR bit is set when a level of the correct polarity is detected on the LOL_FDET_XO interrupt source. The LOL_FDET_XO_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N

1.40 R46 (Offset = 0x2E)

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Table 1-42 R46 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL1_INTRR0x0 LOPL_DPLL1 Interrupt. The LOPL_DPLL1_INTR bit is set when a level of the correct polarity is detected on the LOPL_DPLL1 interrupt source. The LOPL_DPLL1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
6LOFL_DPLL1_INTRR0x0 LOFL_DPLL1 Interrupt. The LOFL_DPLL1_INTR bit is set when a level of the correct polarity is detected on the LOFL_DPLL1 interrupt source. The LOFL_DPLL1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
5HIST1_INTRR0x0 HIST1 Interrupt. The HIST1_INTR bit is set when a level of the correct polarity is detected on the HIST1 interrupt source. The HIST1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
4HLDOVR1_INTRR0x0 HLDOVR1 Interrupt. The HLDOVR1_INTR bit is set when a level of the correct polarity is detected on the HLDOVR1 interrupt source. The HLDOVR1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
3REFSWITCH1_INTRR0x0 REFSWITCH1 Interrupt. The REFSWITCH1_INTR bit is set when a level of the correct polarity is detected on the REFSWITCH1 interrupt source. The REFSWITCH1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
2LOR_MISSCLK1_INTRR0x0 LOR_MISSCLK1 Interrupt. The LOR_MISSCLK1_INTR bit is set when a level of the correct polarity is detected on the LOR_MISSCLK1 interrupt source. The LOR_MISSCLK1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
1LOR_FREQ1_INTRR0x0 LOR_FREQ1 Interrupt. The LOR_FREQ1_INTR bit is set when a level of the correct polarity is detected on the LOR_FREQ1 interrupt source. The LOR_FREQ1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
0LOR_PH1_INTRR0x0 LOR_PH1 Interrupt. The LOR_PH1_INTR bit is set when a level of the correct polarity is detected on the LOR_PH1 interrupt source. The LOR_PH1_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N

1.41 R47 (Offset = 0x2F)

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Table 1-43 R47 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL2_INTRR0x0 LOPL_DPLL2 Interrupt. The LOPL_DPLL2_INTR bit is set when a level of the correct polarity is detected on the LOPL_DPLL2 interrupt source. The LOPL_DPLL2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
6LOFL_DPLL2_INTRR0x0 LOFL_DPLL2 Interrupt. The LOFL_DPLL2_INTR bit is set when a level of the correct polarity is detected on the LOFL_DPLL2 interrupt source. The LOFL_DPLL2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
5HIST2_INTRR0x0 HIST2 Interrupt. The HIST2_INTR bit is set when a level of the correct polarity is detected on the HIST2 interrupt source. The HIST2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
4HLDOVR2_INTRR0x0 HLDOVR2 Interrupt. The HLDOVR2_INTR bit is set when a level of the correct polarity is detected on the HLDOVR2 interrupt source. The HLDOVR2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
3REFSWITCH2_INTRR0x0 REFSWITCH2 Interrupt. The REFSWITCH2_INTR bit is set when a level of the correct polarity is detected on the REFSWITCH2 interrupt source. The REFSWITCH2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
2LOR_MISSCLK2_INTRR0x0 LOR_MISSCLK2 Interrupt. The LOR_MISSCLK2_INTR bit is set when a level of the correct polarity is detected on the LOR_MISSCLK2 interrupt source. The LOR_MISSCLK2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
1LOR_FREQ2_INTRR0x0 LOR_FREQ2 Interrupt. The LOR_FREQ2_INTR bit is set when a level of the correct polarity is detected on the LOR_FREQ2 interrupt source. The LOR_FREQ2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
0LOR_PH2_INTRR0x0 LOR_PH2 Interrupt. The LOR_PH2_INTR bit is set when a level of the correct polarity is detected on the LOR_PH2 interrupt source. The LOR_PH2_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N

1.42 R48 (Offset = 0x30)

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Table 1-44 R48 Field Descriptions
BitFieldTypeResetDescription
7LOPL_DPLL3_INTRR0x0 LOPL_DPLL3 Interrupt. The LOPL_DPLL3_INTR bit is set when a level of the correct polarity is detected on the LOPL_DPLL3 interrupt source. The LOPL_DPLL3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
6LOFL_DPLL3_INTRR0x0 LOFL_DPLL3 Interrupt. The LOFL_DPLL3_INTR bit is set when a level of the correct polarity is detected on the LOFL_DPLL3 interrupt source. The LOFL_DPLL3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
5HIST3_INTRR0x0 HIST3 Interrupt. The HIST3_INTR bit is set when a level of the correct polarity is detected on the HIST3 interrupt source. The HIST3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
4HLDOVR3_INTRR0x0 HLDOVR3 Interrupt. The HLDOVR3_INTR bit is set when a level of the correct polarity is detected on the HLDOVR3 interrupt source. The HLDOVR3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
3REFSWITCH3_INTRR0x0 REFSWITCH3 Interrupt. The REFSWITCH3_INTR bit is set when a level of the correct polarity is detected on the REFSWITCH3 interrupt source. The REFSWITCH3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
2LOR_MISSCLK3_INTRR0x0 LOR_MISSCLK3 Interrupt. The LOR_MISSCLK3_INTR bit is set when a level of the correct polarity is detected on the LOR_MISSCLK3 interrupt source. The LOR_MISSCLK3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
1LOR_FREQ3_INTRR0x0 LOR_FREQ3 Interrupt. The LOR_FREQ3_INTR bit is set when a level of the correct polarity is detected on the LOR_FREQ3 interrupt source. The LOR_FREQ3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N
0LOR_PH3_INTRR0x0 LOR_PH3 Interrupt. The LOR_PH3_INTR bit is set when a level of the correct polarity is detected on the LOR_PH3 interrupt source. The LOR_PH3_INTR bit is cleared by writing a 1 to INT_CLR.
ROM=N, EEPROM=N

1.43 R49 (Offset = 0x31)

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Table 1-45 R49 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3INT_LATCH_OR_LIVER/W0x0 ROM=Y, EEPROM=N
  • 0x0 = Latch Mode
  • 0x1 = Live Mode
2INT_AND_ORR/W0x0 Interrupt AND/OR Combination. If INT_AND_OR is 1, then the interrupts are combined in an AND structure, in which case ALL un-masked interrupt flags must be active in order to generate the interrupt. If INT_AND_OR is 0, then the interrupts are combined in an OR structure, in which case ANY un-masked interrupt flags can generate the interrupt.
ROM=Y, EEPROM=N
  • 0x0 = OR
  • 0x1 = AND
1INT_ENR/W0x0 Interrupt Enable. If INT_EN is 1 then the interrupt circuit is enabled. If INT_EN is 0 the interrupt circuit is disabled. When INT_EN is 0, interrupts cannot be signaled on the GPIOx pins, and the flag registers (*_INTR) will not be updated; however, the live status registers will still reflect the current state of the internal interrupt source signals. To provide an interrupt on a pin, a GPIOx pin must also be configured as interrupt output. Interrupts may be enabled without providing a GPIOx output to allow sticky bits to be set.
ROM=Y, EEPROM=N
0INT_CLRR/WSC0x0 Clears all interrupt flag (*_INTR) registers
ROM=N, EEPROM=N

1.44 R50 (Offset = 0x32)

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Table 1-46 R50 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3REF3_VALID_STATUSR0x0 Status of Reference Input Validation for IN3
ROM=N, EEPROM=N
2REF2_VALID_STATUSR0x0 Status of Reference Input Validation for IN2
ROM=N, EEPROM=N
1REF1_VALID_STATUSR0x0 Status of Reference Input Validation for IN1
ROM=N, EEPROM=N
0REF0_VALID_STATUSR0x0 Status of Reference Input Validation for IN0
ROM=N, EEPROM=N

1.45 R51 (Offset = 0x33)

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Table 1-47 R51 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF3_PH_STATUSR0x0 Status of Reference 3 Phase Validation
ROM=N, EEPROM=N
4RESERVEDR0x0 Reserved
3REF3_FDET_STATUSR0x0 Status of Reference 3 Frequency Validation
ROM=N, EEPROM=N
2REF2_PH_STATUSR0x0 Status of Reference 2 Phase Validation
ROM=N, EEPROM=N
1RESERVEDR0x0 Reserved
0REF2_FDET_STATUSR0x0 Status of Reference 2 Frequency Validation
ROM=N, EEPROM=N

1.46 R52 (Offset = 0x34)

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Table 1-48 R52 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF1_PH_STATUSR0x0 Status of Reference 1 Phase Validation
ROM=N, EEPROM=N
4RESERVEDR0x0 Reserved
3REF1_FDET_STATUSR0x0 Status of Reference 1 Frequency Validation
ROM=N, EEPROM=N
2REF0_PH_STATUSR0x0 Status of Reference 0 Phase Validation
ROM=N, EEPROM=N
1RESERVEDR0x0 Reserved
0REF0_FDET_STATUSR0x0 Status of Reference 0 Frequency Validation
ROM=N, EEPROM=N

1.47 R53 (Offset = 0x35)

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Table 1-49 R53 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4TEC_CNTR_HELDR0x0 TEC Held. Reading back a 1 indicates GPIO or SPI event has latched a holdover value. Will clear to 0 after TEC CNTR LSB is read.
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.48 R54 (Offset = 0x36)

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Table 1-50 R54 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6GPIO0_IN_FLT_ENR/W0x0 Enable GPIO0 Input Pin Deglitch Filter
ROM=Y, EEPROM=N
5:0GPIO0_MODER/W0x0 Select GPIO0 Pin Operating Mode.
ROM=Y, EEPROM=N
  • 0x0 = STATUS or INT, Acts as status or interrupt outputs (See section on STATUS/INTERRUPT)
  • 0x1 = INSEL01_DPLL1, Selects input 0 or input 1 for DPLL1
  • 0x2 = INSEL01_DPLL2, Selects input 0 or input 1 for DPLL2
  • 0x3 = INSEL01_DPLL3, Selects input 0 or input 1 for DPLL3
  • 0x4 = INSEL23_DPLL1, Selects input 2 or input 3 for DPLL1
  • 0x5 = INSEL23_DPLL2, Selects input 2 or input 3 for DPLL2
  • 0x6 = INSEL23_DPLL3, Selects input 2 or input 3 for DPLL3
  • 0x7 = Reserved
  • 0x8 = Reserved
  • 0x9 = Reserved
  • 0xA = Reserved
  • 0xB = Reserved
  • 0xC = Reserved
  • 0xD = INSEL12_DPLL1, Selects input 1 or input 2 for DPLL1
  • 0xE = INSEL12_DPLL2, Selects input 1 or input 2 for DPLL2
  • 0xF = INSEL12_DPLL3, Selects input 1 or input 2 for DPLL3
  • 0x10 = INSEL03_DPLL1, Selects input 0 or input 3 for DPLL1
  • 0x11 = INSEL03_DPLL2, Selects input 0 or input 3 for DPLL2
  • 0x12 = INSEL03_DPLL3, Selects input 0 or input 3 for DPLL3
  • 0x13 = INSEL02_DPLL1, Selects input 0 or input 2 for DPLL1
  • 0x14 = INSEL02_DPLL2, Selects input 0 or input 2 for DPLL2
  • 0x15 = INSEL02_DPLL3, Selects input 0 or input 2 for DPLL3
  • 0x16 = Reserved
  • 0x17 = Reserved
  • 0x18 = Reserved
  • 0x19 = INSEL13_DPLL1, Selects input 1 or input 3 for DPLL1
  • 0x1A = INSEL13_DPLL2, Selects input 1 or input 3 for DPLL2
  • 0x1B = INSEL13_DPLL3, Selects input 1 or input 3 for DPLL3
  • 0x1C = Reserved
  • 0x1D = Reserved
  • 0x1E = Reserved
  • 0x1F = SYNC, Synchronizes selected outputs on a low-to-high pulse. "1" is normal state for outputs. "0" sets outputs in SYNC.
  • 0x20 = SYSREF_REQ, Can request SYSREF pulses on appropriate output channels via low-to-high pulse.
  • 0x21 = FDEV_TRIG_DPLL1, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL1
  • 0x22 = FDEV_TRIG_DPLL2, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL2
  • 0x23 = FDEV_TRIG_DPLL3, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL3
  • 0x24 = FDEV_DIR_DPLL1, FDEV_DIR_DPLL1 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x25 = FDEV_DIR_DPLL2, FDEV_DIR_DPLL2 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x26 = FDEV_DIR_DPLL3, FDEV_DIR_DPLL3 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x27 = TEC_TRIG_SEL

1.49 R55 (Offset = 0x37)

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Table 1-51 R55 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6GPIO1_IN_FLT_ENR/W0x0 Enable GPIO1 Input Pin Deglitch Filter
ROM=Y, EEPROM=N
5:0GPIO1_MODER/W0x0 Select GPIO1 Pin Operating Mode.
ROM=Y, EEPROM=N
  • 0x0 = STATUS or INT, Acts as status or interrupt outputs (See section on STATUS/INTERRUPT)
  • 0x1 = INSEL01_DPLL1, Selects input 0 or input 1 for DPLL1
  • 0x2 = INSEL01_DPLL2, Selects input 0 or input 1 for DPLL2
  • 0x3 = INSEL01_DPLL3, Selects input 0 or input 1 for DPLL3
  • 0x4 = INSEL23_DPLL1, Selects input 2 or input 3 for DPLL1
  • 0x5 = INSEL23_DPLL2, Selects input 2 or input 3 for DPLL2
  • 0x6 = INSEL23_DPLL3, Selects input 2 or input 3 for DPLL3
  • 0x7 = Reserved
  • 0x8 = Reserved
  • 0x9 = Reserved
  • 0xA = Reserved
  • 0xB = Reserved
  • 0xC = Reserved
  • 0xD = INSEL12_DPLL1, Selects input 1 or input 2 for DPLL1
  • 0xE = INSEL12_DPLL2, Selects input 1 or input 2 for DPLL2
  • 0xF = INSEL12_DPLL3, Selects input 1 or input 2 for DPLL3
  • 0x10 = INSEL03_DPLL1, Selects input 0 or input 3 for DPLL1
  • 0x11 = INSEL03_DPLL2, Selects input 0 or input 3 for DPLL2
  • 0x12 = INSEL03_DPLL3, Selects input 0 or input 3 for DPLL3
  • 0x13 = INSEL02_DPLL1, Selects input 0 or input 2 for DPLL1
  • 0x14 = INSEL02_DPLL2, Selects input 0 or input 2 for DPLL2
  • 0x15 = INSEL02_DPLL3, Selects input 0 or input 2 for DPLL3
  • 0x16 = Reserved
  • 0x17 = Reserved
  • 0x18 = Reserved
  • 0x19 = INSEL13_DPLL1, Selects input 1 or input 3 for DPLL1
  • 0x1A = INSEL13_DPLL2, Selects input 1 or input 3 for DPLL2
  • 0x1B = INSEL13_DPLL3, Selects input 1 or input 3 for DPLL3
  • 0x1C = Reserved
  • 0x1D = Reserved
  • 0x1E = Reserved
  • 0x1F = SYNC, Synchronizes selected outputs on a low-to-high pulse. "1" is normal state for outputs. "0" sets outputs in SYNC.
  • 0x20 = SYSREF_REQ, Can request SYSREF pulses on appropriate output channels via low-to-high pulse.
  • 0x21 = FDEV_TRIG_DPLL1, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL1
  • 0x22 = FDEV_TRIG_DPLL2, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL2
  • 0x23 = FDEV_TRIG_DPLL3, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL3
  • 0x24 = FDEV_DIR_DPLL1, FDEV_DIR_DPLL1 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x25 = FDEV_DIR_DPLL2, FDEV_DIR_DPLL2 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x26 = FDEV_DIR_DPLL3, FDEV_DIR_DPLL3 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x27 = TEC_TRIG_SEL

1.50 R56 (Offset = 0x38)

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Table 1-52 R56 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6GPIO2_IN_FLT_ENR/W0x0 Enable GPIO2 Input Pin Deglitch Filter
ROM=Y, EEPROM=N
5:0GPIO2_MODER/W0x0 Select GPIO2 Pin Operating Mode.
ROM=Y, EEPROM=N
  • 0x0 = STATUS or INT, Acts as status or interrupt outputs (See section on STATUS/INTERRUPT)
  • 0x1 = INSEL01_DPLL1, Selects input 0 or input 1 for DPLL1
  • 0x2 = INSEL01_DPLL2, Selects input 0 or input 1 for DPLL2
  • 0x3 = INSEL01_DPLL3, Selects input 0 or input 1 for DPLL3
  • 0x4 = INSEL23_DPLL1, Selects input 2 or input 3 for DPLL1
  • 0x5 = INSEL23_DPLL2, Selects input 2 or input 3 for DPLL2
  • 0x6 = INSEL23_DPLL3, Selects input 2 or input 3 for DPLL3
  • 0x7 = Reserved
  • 0x8 = Reserved
  • 0x9 = Reserved
  • 0xA = Reserved
  • 0xB = Reserved
  • 0xC = Reserved
  • 0xD = INSEL12_DPLL1, Selects input 1 or input 2 for DPLL1
  • 0xE = INSEL12_DPLL2, Selects input 1 or input 2 for DPLL2
  • 0xF = INSEL12_DPLL3, Selects input 1 or input 2 for DPLL3
  • 0x10 = INSEL03_DPLL1, Selects input 0 or input 3 for DPLL1
  • 0x11 = INSEL03_DPLL2, Selects input 0 or input 3 for DPLL2
  • 0x12 = INSEL03_DPLL3, Selects input 0 or input 3 for DPLL3
  • 0x13 = INSEL02_DPLL1, Selects input 0 or input 2 for DPLL1
  • 0x14 = INSEL02_DPLL2, Selects input 0 or input 2 for DPLL2
  • 0x15 = INSEL02_DPLL3, Selects input 0 or input 2 for DPLL3
  • 0x16 = Reserved
  • 0x17 = Reserved
  • 0x18 = Reserved
  • 0x19 = INSEL13_DPLL1, Selects input 1 or input 3 for DPLL1
  • 0x1A = INSEL13_DPLL2, Selects input 1 or input 3 for DPLL2
  • 0x1B = INSEL13_DPLL3, Selects input 1 or input 3 for DPLL3
  • 0x1C = Reserved
  • 0x1D = Reserved
  • 0x1E = Reserved
  • 0x1F = SYNC, Synchronizes selected outputs on a low-to-high pulse. "1" is normal state for outputs. "0" sets outputs in SYNC.
  • 0x20 = SYSREF_REQ, Can request SYSREF pulses on appropriate output channels via low-to-high pulse.
  • 0x21 = FDEV_TRIG_DPLL1, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL1
  • 0x22 = FDEV_TRIG_DPLL2, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL2
  • 0x23 = FDEV_TRIG_DPLL3, A rising edge will trigger a frequency change based on the FDEV_DIR_DPLL3
  • 0x24 = FDEV_DIR_DPLL1, FDEV_DIR_DPLL1 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x25 = FDEV_DIR_DPLL2, FDEV_DIR_DPLL2 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x26 = FDEV_DIR_DPLL3, FDEV_DIR_DPLL3 will determine the direction of the FDEV trigger. 0 = Negative and 1 = Positive
  • 0x27 = TEC_TRIG_SEL

1.51 R57 (Offset = 0x39)

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Table 1-53 R57 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0GPIO0_SELR/W0x0 GPIO0 Status Signal Select.
ROM=Y, EEPROM=N
  • 0x0 = XO Loss of Signal (LOS)
  • 0x1 = APLL1 Loss of Lock (LOL)
  • 0x2 = APLL2 Loss of Lock (LOL)
  • 0x3 = APLL3 Loss of Lock (LOL)
  • 0x4 = DPLL1 Loss of Phase Lock (LOPL)
  • 0x5 = DPLL1 Loss of Frequency Lock (LOFL)
  • 0x6 = PLL1 LOL | DPLL1 LOPL | DPLL1 LOFL
  • 0x7 = DPLL2 Loss of Phase Lock (LOPL)
  • 0x8 = DPLL2 Loss of Frequency Lock (LOFL)
  • 0x9 = PLL2 LOL | DPLL2 LOPL | DPLL2 LOFL
  • 0xA = DPLL3 Loss of Phase Lock (LOPL)
  • 0xB = DPLL3 Loss of Frequency Lock (LOFL)
  • 0xC = PLL3 LOL | DPLL3 LOPL | DPLL3 LOFL
  • 0xD = DPLL1 | DPLL2 | DPLL3 LOL
  • 0xE = Interrupt (INTR). Derived from INT_FLAG register bits.
  • 0xF = SPI Readback Data (SDO)
  • 0x10 = Reserved
  • 0x11 = Reserved
  • 0x12 = Reserved
  • 0x13 = Reserved
  • 0x14 = Reserved
  • 0x15 = DPLL1 REF0 Selected
  • 0x16 = DPLL1 REF1 Selected
  • 0x17 = DPLL1 REF2 Selected
  • 0x18 = DPLL1 REF3 Selected
  • 0x19 = Reserved
  • 0x1A = DPLL1 Holdover Active
  • 0x1B = DPLL2 REF0 Selected
  • 0x1C = DPLL2 REF1 Selected
  • 0x1D = DPLL2 REF2 Selected
  • 0x1E = DPLL2 REF3 Selected
  • 0x1F = Reserved
  • 0x20 = DPLL2 Holdover Active
  • 0x21 = DPLL3 REF0 Selected
  • 0x22 = DPLL3 REF1 Selected
  • 0x23 = DPLL3 REF2 Selected
  • 0x24 = DPLL3 REF3 Selected
  • 0x25 = Reserved
  • 0x26 = DPLL3 Holdover Active
  • 0x27 = REF0 Frequency Monitor
  • 0x28 = REF1 Frequency Monitor
  • 0x29 = REF2 Frequency Monitor
  • 0x2A = REF3 Frequency Monitor
  • 0x2B = Reserved
  • 0x2C = REF0 Missing Clock Monitor
  • 0x2D = REF1 Missing Clock Monitor
  • 0x2E = REF2 Missing Clock Monitor
  • 0x2F = REF3 Missing Clock Monitor
  • 0x30 = Reserved
  • 0x31 = Reserved
  • 0x32 = Reserved
  • 0x33 = Reserved
  • 0x34 = Reserved
  • 0x35 = Reserved
  • 0x36 = Reserved
  • 0x37 = Reserved
  • 0x38 = Reserved
  • 0x39 = Reserved
  • 0x3A = Reserved
  • 0x3B = REF0 Phase Validation Monitor
  • 0x3C = REF1 Phase Validation Monitor
  • 0x3D = REF2 Phase Validation Monitor
  • 0x3E = REF3 Phase Validation Monitor
  • 0x3F = Reserved
  • 0x40 = Reserved
  • 0x41 = Reserved
  • 0x42 = Reserved
  • 0x43 = Reserved
  • 0x44 = Reserved
  • 0x45 = Reserved
  • 0x46 = Reserved
  • 0x47 = Reserved
  • 0x48 = Reserved
  • 0x49 = Reserved
  • 0x4A = Reserved
  • 0x4B = Reserved
  • 0x4C = Reserved
  • 0x4D = Reserved
  • 0x4E = Reserved
  • 0x4F = Reserved
  • 0x50 = PLL1 N-Divider Divided By 2
  • 0x51 = PLL2 N-Divider Divided By 2
  • 0x52 = PLL3 N-Divider Divided By 2
  • 0x53 = PLL1 R-Divider Divided By 2
  • 0x54 = PLL2 R-Divider Divided By 2
  • 0x55 = PLL3 R-Divider Divided By 2
  • 0x56 = Reserved
  • 0x57 = Reserved
  • 0x58 = Reserved
  • 0x59 = REF0 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5A = REF1 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5B = REF2 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5C = REF3 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5D = Reserved
  • 0x5E = TDC1 R-Divider Divided By 2
  • 0x5F = Reserved
  • 0x60 = TDC1 FB-Divider Divided By 2
  • 0x61 = TDC2 R-Divider Divided By 2
  • 0x62 = Reserved
  • 0x63 = TDC2 FB-Divider Divided By 2
  • 0x64 = TDC3 R-Divider Divided By 2
  • 0x65 = Reserved
  • 0x66 = TDC3 FB-Divider Divided By 2
  • 0x67 = Reserved
  • 0x68 = Reserved
  • 0x69 = Reserved
  • 0x6A = Reserved
  • 0x6B = Reserved
  • 0x6C = Reserved
  • 0x6D = Reserved
  • 0x6E = Reserved
  • 0x6F = Reserved
  • 0x70 = Reserved
  • 0x71 = Reserved
  • 0x72 = Reserved

1.52 R58 (Offset = 0x3A)

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Table 1-54 R58 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0GPIO1_SELR/W0x0 GPIO1 Status Signal Select.
ROM=Y, EEPROM=N
  • 0x0 = XO Loss of Signal (LOS)
  • 0x1 = APLL1 Loss of Lock (LOL)
  • 0x2 = APLL2 Loss of Lock (LOL)
  • 0x3 = APLL3 Loss of Lock (LOL)
  • 0x4 = DPLL1 Loss of Phase Lock (LOPL)
  • 0x5 = DPLL1 Loss of Frequency Lock (LOFL)
  • 0x6 = PLL1 LOL | DPLL1 LOPL | DPLL1 LOFL
  • 0x7 = DPLL2 Loss of Phase Lock (LOPL)
  • 0x8 = DPLL2 Loss of Frequency Lock (LOFL)
  • 0x9 = PLL2 LOL | DPLL2 LOPL | DPLL2 LOFL
  • 0xA = DPLL3 Loss of Phase Lock (LOPL)
  • 0xB = DPLL3 Loss of Frequency Lock (LOFL)
  • 0xC = PLL3 LOL | DPLL3 LOPL | DPLL3 LOFL
  • 0xD = DPLL1 | DPLL2 | DPLL3 LOL
  • 0xE = Interrupt (INTR). Derived from INT_FLAG register bits.
  • 0xF = SPI Readback Data (SDO)
  • 0x10 = Reserved
  • 0x11 = Reserved
  • 0x12 = Reserved
  • 0x13 = Reserved
  • 0x14 = Reserved
  • 0x15 = DPLL1 REF0 Selected
  • 0x16 = DPLL1 REF1 Selected
  • 0x17 = DPLL1 REF2 Selected
  • 0x18 = DPLL1 REF3 Selected
  • 0x19 = Reserved
  • 0x1A = DPLL1 Holdover Active
  • 0x1B = DPLL2 REF0 Selected
  • 0x1C = DPLL2 REF1 Selected
  • 0x1D = DPLL2 REF2 Selected
  • 0x1E = DPLL2 REF3 Selected
  • 0x1F = Reserved
  • 0x20 = DPLL2 Holdover Active
  • 0x21 = DPLL3 REF0 Selected
  • 0x22 = DPLL3 REF1 Selected
  • 0x23 = DPLL3 REF2 Selected
  • 0x24 = DPLL3 REF3 Selected
  • 0x25 = Reserved
  • 0x26 = DPLL3 Holdover Active
  • 0x27 = REF0 Frequency Monitor
  • 0x28 = REF1 Frequency Monitor
  • 0x29 = REF2 Frequency Monitor
  • 0x2A = REF3 Frequency Monitor
  • 0x2B = Reserved
  • 0x2C = REF0 Missing Clock Monitor
  • 0x2D = REF1 Missing Clock Monitor
  • 0x2E = REF2 Missing Clock Monitor
  • 0x2F = REF3 Missing Clock Monitor
  • 0x30 = Reserved
  • 0x31 = Reserved
  • 0x32 = Reserved
  • 0x33 = Reserved
  • 0x34 = Reserved
  • 0x35 = Reserved
  • 0x36 = Reserved
  • 0x37 = Reserved
  • 0x38 = Reserved
  • 0x39 = Reserved
  • 0x3A = Reserved
  • 0x3B = REF0 Phase Validation Monitor
  • 0x3C = REF1 Phase Validation Monitor
  • 0x3D = REF2 Phase Validation Monitor
  • 0x3E = REF3 Phase Validation Monitor
  • 0x3F = Reserved
  • 0x40 = Reserved
  • 0x41 = Reserved
  • 0x42 = Reserved
  • 0x43 = Reserved
  • 0x44 = Reserved
  • 0x45 = Reserved
  • 0x46 = Reserved
  • 0x47 = Reserved
  • 0x48 = Reserved
  • 0x49 = Reserved
  • 0x4A = Reserved
  • 0x4B = Reserved
  • 0x4C = Reserved
  • 0x4D = Reserved
  • 0x4E = Reserved
  • 0x4F = Reserved
  • 0x50 = PLL1 N-Divider Divided By 2
  • 0x51 = PLL2 N-Divider Divided By 2
  • 0x52 = PLL3 N-Divider Divided By 2
  • 0x53 = PLL1 R-Divider Divided By 2
  • 0x54 = PLL2 R-Divider Divided By 2
  • 0x55 = PLL3 R-Divider Divided By 2
  • 0x56 = Reserved
  • 0x57 = Reserved
  • 0x58 = Reserved
  • 0x59 = REF0 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5A = REF1 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5B = REF2 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5C = REF3 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5D = Reserved
  • 0x5E = TDC1 R-Divider Divided By 2
  • 0x5F = Reserved
  • 0x60 = TDC1 FB-Divider Divided By 2
  • 0x61 = TDC2 R-Divider Divided By 2
  • 0x62 = Reserved
  • 0x63 = TDC2 FB-Divider Divided By 2
  • 0x64 = TDC3 R-Divider Divided By 2
  • 0x65 = Reserved
  • 0x66 = TDC3 FB-Divider Divided By 2
  • 0x67 = Reserved
  • 0x68 = Reserved
  • 0x69 = Reserved
  • 0x6A = Reserved
  • 0x6B = Reserved
  • 0x6C = Reserved
  • 0x6D = Reserved
  • 0x6E = Reserved
  • 0x6F = Reserved
  • 0x70 = Reserved
  • 0x71 = Reserved
  • 0x72 = Reserved
  • 0x73 = Continuous SYSREF / 1-PPS from selected SYSREF DIV

1.53 R59 (Offset = 0x3B)

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Table 1-55 R59 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0GPIO2_SELR/W0x0 GPIO2 Status Signal Select.
ROM=Y, EEPROM=N
  • 0x0 = XO Loss of Signal (LOS)
  • 0x1 = APLL1 Loss of Lock (LOL)
  • 0x2 = APLL2 Loss of Lock (LOL)
  • 0x3 = APLL3 Loss of Lock (LOL)
  • 0x4 = DPLL1 Loss of Phase Lock (LOPL)
  • 0x5 = DPLL1 Loss of Frequency Lock (LOFL)
  • 0x6 = PLL1 LOL | DPLL1 LOPL | DPLL1 LOFL
  • 0x7 = DPLL2 Loss of Phase Lock (LOPL)
  • 0x8 = DPLL2 Loss of Frequency Lock (LOFL)
  • 0x9 = PLL2 LOL | DPLL2 LOPL | DPLL2 LOFL
  • 0xA = DPLL3 Loss of Phase Lock (LOPL)
  • 0xB = DPLL3 Loss of Frequency Lock (LOFL)
  • 0xC = PLL3 LOL | DPLL3 LOPL | DPLL3 LOFL
  • 0xD = DPLL1 | DPLL2 | DPLL3 LOL
  • 0xE = Interrupt (INTR). Derived from INT_FLAG register bits.
  • 0xF = SPI Readback Data (SDO)
  • 0x10 = Reserved
  • 0x11 = Reserved
  • 0x12 = Reserved
  • 0x13 = Reserved
  • 0x14 = Reserved
  • 0x15 = DPLL1 REF0 Selected
  • 0x16 = DPLL1 REF1 Selected
  • 0x17 = DPLL1 REF2 Selected
  • 0x18 = DPLL1 REF3 Selected
  • 0x19 = Reserved
  • 0x1A = DPLL1 Holdover Active
  • 0x1B = DPLL2 REF0 Selected
  • 0x1C = DPLL2 REF1 Selected
  • 0x1D = DPLL2 REF2 Selected
  • 0x1E = DPLL2 REF3 Selected
  • 0x1F = Reserved
  • 0x20 = DPLL2 Holdover Active
  • 0x21 = DPLL3 REF0 Selected
  • 0x22 = DPLL3 REF1 Selected
  • 0x23 = DPLL3 REF2 Selected
  • 0x24 = DPLL3 REF3 Selected
  • 0x25 = Reserved
  • 0x26 = DPLL3 Holdover Active
  • 0x27 = REF0 Frequency Monitor
  • 0x28 = REF1 Frequency Monitor
  • 0x29 = REF2 Frequency Monitor
  • 0x2A = REF3 Frequency Monitor
  • 0x2B = Reserved
  • 0x2C = REF0 Missing Clock Monitor
  • 0x2D = REF1 Missing Clock Monitor
  • 0x2E = REF2 Missing Clock Monitor
  • 0x2F = REF3 Missing Clock Monitor
  • 0x30 = Reserved
  • 0x31 = Reserved
  • 0x32 = Reserved
  • 0x33 = Reserved
  • 0x34 = Reserved
  • 0x35 = Reserved
  • 0x36 = Reserved
  • 0x37 = Reserved
  • 0x38 = Reserved
  • 0x39 = Reserved
  • 0x3A = Reserved
  • 0x3B = REF0 Phase Validation Monitor
  • 0x3C = REF1 Phase Validation Monitor
  • 0x3D = REF2 Phase Validation Monitor
  • 0x3E = REF3 Phase Validation Monitor
  • 0x3F = Reserved
  • 0x40 = Reserved
  • 0x41 = Reserved
  • 0x42 = Reserved
  • 0x43 = Reserved
  • 0x44 = Reserved
  • 0x45 = Reserved
  • 0x46 = Reserved
  • 0x47 = Reserved
  • 0x48 = Reserved
  • 0x49 = Reserved
  • 0x4A = Reserved
  • 0x4B = Reserved
  • 0x4C = Reserved
  • 0x4D = Reserved
  • 0x4E = Reserved
  • 0x4F = Reserved
  • 0x50 = PLL1 N-Divider Divided By 2
  • 0x51 = PLL2 N-Divider Divided By 2
  • 0x52 = PLL3 N-Divider Divided By 2
  • 0x53 = PLL1 R-Divider Divided By 2
  • 0x54 = PLL2 R-Divider Divided By 2
  • 0x55 = PLL3 R-Divider Divided By 2
  • 0x56 = Reserved
  • 0x57 = Reserved
  • 0x58 = Reserved
  • 0x59 = REF0 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5A = REF1 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5B = REF2 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5C = REF3 Monitor Divider Output Divided By 2 / REFx_DET_CLK_DIV
  • 0x5D = Reserved
  • 0x5E = TDC1 R-Divider Divided By 2
  • 0x5F = Reserved
  • 0x60 = TDC1 FB-Divider Divided By 2
  • 0x61 = TDC2 R-Divider Divided By 2
  • 0x62 = Reserved
  • 0x63 = TDC2 FB-Divider Divided By 2
  • 0x64 = TDC3 R-Divider Divided By 2
  • 0x65 = Reserved
  • 0x66 = TDC3 FB-Divider Divided By 2
  • 0x67 = Reserved
  • 0x68 = Reserved
  • 0x69 = Reserved
  • 0x6A = Reserved
  • 0x6B = Reserved
  • 0x6C = Reserved
  • 0x6D = Reserved
  • 0x6E = Reserved
  • 0x6F = Reserved
  • 0x70 = Reserved
  • 0x71 = Reserved
  • 0x72 = Reserved
  • 0x73 = Continuous SYSREF / 1-PPS from selected SYSREF DIV

1.54 R60 (Offset = 0x3C)

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Table 1-56 R60 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5GPIO0_OPENDR/W0x0 GPIO0 Open Drain Enable
ROM=Y, EEPROM=N
  • 0x0 = CMOS
  • 0x1 = NMOS open drain. External pull-up from 1.8 V to 5.5 V supply rail required.
4GPIO1_OPENDR/W0x0 GPIO1 Open Drain Enable
ROM=Y, EEPROM=N
  • 0x0 = CMOS
  • 0x1 = NMOS open drain. External pull-up from 1.8 V to 5.5 V supply rail required.
3GPIO2_OPENDR/W0x0 GPIO2 Open Drain Enable
ROM=Y, EEPROM=N
  • 0x0 = CMOS
  • 0x1 = NMOS open drain. External pull-up from 1.8 V to 5.5 V supply rail required.
2GPIO0_POLR/W0x0 GPIO0 Status Output Polarity. The GPIO0_STAT_POL bit defines the polarity of information presented on the GPIO0 output. If GPIO0_STAT_POL is set to 1, then GPIO0 is active high. If GPIO0_STAT_POL is 0, then GPIO0 is active low.
ROM=Y, EEPROM=N
  • 0x0 = Active High
  • 0x1 = Active Low
1GPIO1_POLR/W0x0 GPIO1 Status Output Polarity. The GPIO1_STAT_POL bit defines the polarity of information presented on the GPIO1 output. If GPIO1_STAT_POL is set to 1, then GPIO1 is active high. If GPIO1_STAT_POL is 0, then GPIO1 is active low.
ROM=Y, EEPROM=N
  • 0x0 = Active High
  • 0x1 = Active Low
0GPIO2_POLR/W0x0 GPIO2 Status Output Polarity. The GPIO2_STAT_POL bit defines the polarity of information presented on the GPIO2 output. If GPIO2_STAT_POL is set to 1, then GPIO2 is active high. If GPIO2_STAT_POL is 0, then GPIO2 is active low.
ROM=Y, EEPROM=N
  • 0x0 = Active High
  • 0x1 = Active Low

1.55 R61 (Offset = 0x3D)

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Table 1-57 R61 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:2GPIO_SYSREF_SELR/W0x0 Select SYSREF divider output for GPIO output. When GPIOx_SEL chooses SYSREF divider, this is the SYSREF divider output on the GPIO. This signal is continuous. This could be used for low frequency outputs such as 1-PPS or 8 kHz as a 3.3-V LVCMOS signal. Select SYSREF divider output after static digital delay but before the analog and digital delay and pulser.
ROM=Y, EEPROM=N
  • 0x0 = OUT_0_1
  • 0x1 = OUT_4_5
  • 0x2 = OUT_6_7
  • 0x3 = OUT_8_9
  • 0x4 = OUT_10_11
  • 0x5 = OUT_12_13
  • 0x6 = NA
  • 0x7 = NA
1MUTE_DPLL3_PHLOCKR/W0x0 DPLL3 mute enabled during phase lock. Muted outputs will start clocking glitch free once achieving lock status. PLL3 outputs will be muted even if DPLL3_EN = 0.
ROM=Y, EEPROM=Y
0MUTE_DPLL3_FRLOCKR/W0x0 DPLL3 mute enabled during dpll lock. Muted outputs will start clocking glitch free once achieving lock status. PLL3 outputs will be muted even if DPLL3_EN = 0.
ROM=Y, EEPROM=Y

1.56 R62 (Offset = 0x3E)

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Table 1-58 R62 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5MUTE_DPLL2_PHLOCKR/W0x0 DPLL2 mute enabled during phase lock. Muted outputs will start clocking glitch free once achieving lock status. PLL2 outputs will be muted even if DPLL2_EN = 0.
ROM=Y, EEPROM=Y
4MUTE_DPLL2_FRLOCKR/W0x0 DPLL2 mute enabled during dpll lock. Muted outputs will start clocking glitch free once achieving lock status. PLL2 outputs will be muted even if DPLL2_EN = 0.
ROM=Y, EEPROM=Y
3MUTE_APLL2_LOCKR/W0x0 APLL2 mute enabled during PLL lock. Muted outputs will start clocking glitch free once achieving lock status.
ROM=Y, EEPROM=Y
2MUTE_DPLL1_PHLOCKR/W0x0 DPLL1 mute enabled during phase lock. Muted outputs will start clocking glitch free once achieving lock status.
ROM=Y, EEPROM=Y
1MUTE_DPLL1_FRLOCKR/W0x0 DPLL1 mute enabled during dpll lock. Muted outputs will start clocking glitch free once achieving lock status.
ROM=Y, EEPROM=Y
0MUTE_APLL1_LOCKR/W0x0 APLL1 mute enabled during PLL lock. Muted outputs will start clocking glitch free once achieving lock status.
ROM=Y, EEPROM=Y

1.57 R63 (Offset = 0x3F)

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Table 1-59 R63 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4XO_FDET_BYPR/W0x0 Frequency Detector Bypass. When XO_FDET_BYP is set to 1, the output of the XO frequency detector is ignored.
ROM=Y, EEPROM=N
3:0XO_ITYPER/W0x0 XO interface type control.
ROM=Y, EEPROM=Y
  • 0x0 = DC (ext term)
  • 0x1 = AC (ext term)
  • 0x3 = AC (int 100 Ω to GND)
  • 0x4 = DC (int 50 Ω to GND)
  • 0x5 = AC (int 50 Ω to GND)
  • 0x8 = LVCMOS
  • 0xC = LVCMOS (int 50 Ω)

1.58 R64 (Offset = 0x40)

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Table 1-60 R64 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0XO_OUT_BUF_ENR/W0x0 Bit position enables XO Output Buffer path to:
[0] The XO Freq Detector
[1] APLL1 REF
[2] APLL2 REF
[3] APLL3 REF, and
[4] OUT0_1
ROM=Y, EEPROM=Y

1.59 R65 (Offset = 0x41)

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Table 1-61 R65 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF3_ITYPER/W0x0 To be updated. REF3 interface type control.
ROM=Y, EEPROM=N
  • 0x0 = DIFFin, ext DC, ext term
  • 0x1 = DIFFin, ext AC, ext term
  • 0x2 = DIFFin, ext DC, int 100 Ω diff
  • 0x3 = DIFFin, ext AC, int 100 Ω diff
  • 0x4 = DIFFin, ext DC, int 50 Ω to GND
  • 0x5 = DIFFin, ext AC, int 50 Ω to GND
  • 0x8 = CMOS, ext DC, int AC couple, 70 mV margin
  • 0xC = S-E, ext DC, int AC couple, 70 mV margin, int 50 Ω to GND
  • 0x18 = CMOS, ext DC, int DC couple, 150 mV hysteresis
  • 0x23 = DIFFin, ext AC/DC, int 100 Ω diff, 210 mV margin
  • 0x28 = CMOS, ext DC, int AC couple, 210 mV margin
  • 0x38 = CMOS, ext DC, int DC couple, 0 mV hysteresis

1.60 R66 (Offset = 0x42)

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Table 1-62 R66 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF2_ITYPER/W0x0 To be updated. REF2 interface type control.
ROM=Y, EEPROM=N
  • 0x0 = DIFFin, ext DC, ext term
  • 0x1 = DIFFin, ext AC, ext term
  • 0x2 = DIFFin, ext DC, int 100 Ω diff
  • 0x3 = DIFFin, ext AC, int 100 Ω diff
  • 0x4 = DIFFin, ext DC, int 50 Ω to GND
  • 0x5 = DIFFin, ext AC, int 50 Ω to GND
  • 0x8 = CMOS, ext DC, int AC couple, 70 mV margin
  • 0xC = S-E, ext DC, int AC couple, 70 mV margin, int 50 Ω to GND
  • 0x18 = CMOS, ext DC, int DC couple, 150 mV hysteresis
  • 0x23 = DIFFin, ext AC/DC, int 100 Ω diff, 210 mV margin
  • 0x28 = CMOS, ext DC, int AC couple, 210 mV margin
  • 0x38 = CMOS, ext DC, int DC couple, 0 mV hysteresis

1.61 R67 (Offset = 0x43)

Return to the Summary Table.

Table 1-63 R67 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF1_ITYPER/W0x0 REF1 interface type control.
ROM=Y, EEPROM=N
  • 0x0 = DIFFin, ext DC, ext term
  • 0x1 = DIFFin, ext AC, ext term
  • 0x2 = DIFFin, ext DC, int 100 Ω diff
  • 0x3 = DIFFin, ext AC, int 100 Ω diff
  • 0x4 = DIFFin, ext DC, int 50 Ω to GND
  • 0x5 = DIFFin, ext AC, int 50 Ω to GND
  • 0x8 = CMOS, ext DC, int AC couple, 70 mV margin
  • 0xC = S-E, ext DC, int AC couple, 70 mV margin, int 50 Ω to GND
  • 0x18 = CMOS, ext DC, int DC couple, 150 mV hysteresis
  • 0x23 = DIFFin, ext AC/DC, int 100 Ω diff, 210 mV margin
  • 0x28 = CMOS, ext DC, int AC couple, 210 mV margin
  • 0x38 = CMOS, ext DC, int DC couple, 0 mV hysteresis

1.62 R68 (Offset = 0x44)

Return to the Summary Table.

Table 1-64 R68 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF0_ITYPER/W0x0 REF0 interface type control.
ROM=Y, EEPROM=N
  • 0x0 = DIFFin, ext DC, ext term
  • 0x1 = DIFFin, ext AC, ext term
  • 0x2 = DIFFin, ext DC, int 100 Ω diff
  • 0x3 = DIFFin, ext AC, int 100 Ω diff
  • 0x4 = DIFFin, ext DC, int 50 Ω to GND
  • 0x5 = DIFFin, ext AC, int 50 Ω to GND
  • 0x8 = CMOS, ext DC, int AC couple, 70 mV margin
  • 0xC = S-E, ext DC, int AC couple, 70 mV margin, int 50 Ω to GND
  • 0x18 = CMOS, ext DC, int DC couple, 150 mV hysteresis
  • 0x23 = DIFFin, ext AC/DC, int 100 Ω diff, 210 mV margin
  • 0x28 = CMOS, ext DC, int AC couple, 210 mV margin
  • 0x38 = CMOS, ext DC, int DC couple, 0 mV hysteresis

1.63 R70 (Offset = 0x46)

Return to the Summary Table.

Table 1-65 R70 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0STATUS_MUX_DIV2_ENR/W0x0 Enable all DivideBy2 clocks for Status MUX debug signals
ROM=N, EEPROM=N

1.64 R75 (Offset = 0x4B)

Return to the Summary Table.

Table 1-66 R75 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6TDC3_ZDM_BYPASS_FB_DIVR/W0x0 Selects TDC3 feedback input source
ROM=Y, EEPROM=N
  • 0x0 = Select FB Divider
  • 0x1 = Bypass FB Divider
5TDC3_ZDM_FB_PRE_BYPR/W0x0 Bypasses TDC3 feedback divider when using ZDM with DPLL3.
ROM=Y, EEPROM=N
  • 0x0 = ZDM disabled
  • 0x1 = ZDM enable
4:3TDC3_IN_SELR/W0x0 Selects TDC3 zero delay input
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = OUT_10_11_ZD_FB
  • 0x2 = OUT_0_1_ZD_FB
  • 0x3 = VCO3 direct (ZDM disabled)
2:0TDC3_IN_DRV_SELR/W0x0 Enables zero delay input mux output
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = ZDM disabled
  • 0x3 = Reserved
  • 0x4 = Reserved
  • 0x5 = ZDM enabled
  • 0x6 = Reserved
  • 0x7 = Reserved

1.65 R76 (Offset = 0x4C)

Return to the Summary Table.

Table 1-67 R76 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6TDC2_ZDM_BYPASS_FB_DIVR/W0x0 Selects TDC feedback input. 0=FB_DIV, 1=ZD bypass FBDIV
ROM=Y, EEPROM=N
  • 0x0 = Select FB Divider
  • 0x1 = Bypass FB Divider
5TDC2_ZDM_FB_PRE_BYPR/W0x0 Bypasses TDC2 feedback divider when using ZDM with DPLL2.
ROM=Y, EEPROM=N
  • 0x0 = ZDM disabled
  • 0x1 = ZDM enable
4:3TDC2_IN_SELR/W0x0 Selects zero delay input
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = OUT_4_5_ZD_FB
  • 0x2 = OUT_0_1_ZD_FB
  • 0x3 = VCO2 direct (ZDM disabled)
2:0TDC2_IN_DRV_SELR/W0x0 Enables zero delay input mux output
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = ZDM disabled
  • 0x3 = Reserved
  • 0x4 = Reserved
  • 0x5 = ZDM enabled
  • 0x6 = Reserved
  • 0x7 = Reserved

1.66 R77 (Offset = 0x4D)

Return to the Summary Table.

Table 1-68 R77 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6TDC1_ZDM_BYPASS_FB_DIVR/W0x0 Selects TDC feedback input. 0=FB_DIV, 1=ZD bypass FBDIV
ROM=Y, EEPROM=N
  • 0x0 = Select FB Divider
  • 0x1 = Bypass FB Divider
5TDC1_ZDM_FB_PRE_BYPR/W0x0 Bypasses TDC1 feedback divider when using ZDM with DPLL1.
ROM=Y, EEPROM=N
  • 0x0 = ZDM disabled
  • 0x1 = ZDM enable
4:3TDC1_IN_SELR/W0x0 Selects which output group to feedback for zero delay mode.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = OUT_0_1_ZD_FB
  • 0x3 = VCO1 direct (ZDM disabled)
2:0TDC1_IN_DRV_SELR/W0x0 Enables zero delay input mux output
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = ZDM disabled
  • 0x3 = Reserved
  • 0x4 = Reserved
  • 0x5 = ZDM enabled
  • 0x6 = Reserved
  • 0x7 = Reserved

1.67 R78 (Offset = 0x4E)

Return to the Summary Table.

Table 1-69 R78 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF_OUT01_ENR/W0x0 Ref to OUT0_1 Enable. Enables the path for a reference clock (selected by REF_2OUT01_SEL) to be available for selection at OUT0_1.
ROM=Y, EEPROM=N
4:0REF_OUT01_SELR/W0x0 Ref to OUT0_1 Select. Selects one reference clock which will be fed to the input of OUT0_1 (if path enabled by REF_2OUT01_EN).
ROM=Y, EEPROM=N
  • 0x0 = OFF
  • 0x1 = REF0
  • 0x2 = REF1
  • 0x4 = REF2
  • 0x8 = REF3

1.68 R79 (Offset = 0x4F)

Return to the Summary Table.

Table 1-70 R79 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF0_EARLY_DET_ENR/W0x0 REF0 Early Clock Detect Enable
ROM=Y, EEPROM=N
4REF0_PH_VALID_ENR/W0x0 REF0 Phase Validation Enable
ROM=Y, EEPROM=N
3REF0_VALTMR_ENR/W0x0 REF0 Validation Timer Enable
ROM=Y, EEPROM=N
2REF0_PPM_ENR/W0x0 REF0 Freq ppm Enable
ROM=Y, EEPROM=N
1REF0_MISSCLK_ENR/W0x0 REF0 Missing Clock Detect Enable
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.69 R80 (Offset = 0x50)

Return to the Summary Table.

Table 1-71 R80 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF1_EARLY_DET_ENR/W0x0 REF1 Early Clock Detect Enable
ROM=Y, EEPROM=N
4REF1_PH_VALID_ENR/W0x0 REF1 Phase Validation Enable
ROM=Y, EEPROM=N
3REF1_VALTMR_ENR/W0x0 REF1 Validation Timer Enable
ROM=Y, EEPROM=N
2REF1_PPM_ENR/W0x0 REF1 Freq ppm Enable
ROM=Y, EEPROM=N
1REF1_MISSCLK_ENR/W0x0 REF1 Missing Clock Detect Enable
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.70 R81 (Offset = 0x51)

Return to the Summary Table.

Table 1-72 R81 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF2_EARLY_DET_ENR/W0x0 REF2 Early Clock Detect Enable
ROM=Y, EEPROM=N
4REF2_PH_VALID_ENR/W0x0 REF2 Phase Validation Enable
ROM=Y, EEPROM=N
3REF2_VALTMR_ENR/W0x0 REF2 Validation Timer Enable
ROM=Y, EEPROM=N
2REF2_PPM_ENR/W0x0 REF2 Freq ppm Enable
ROM=Y, EEPROM=N
1REF2_MISSCLK_ENR/W0x0 REF2 Missing Clock Detect Enable
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.71 R82 (Offset = 0x52)

Return to the Summary Table.

Table 1-73 R82 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5REF3_EARLY_DET_ENR/W0x0 REF3 Early Clock Detect Enable
ROM=Y, EEPROM=N
4REF3_PH_VALID_ENR/W0x0 REF3 Phase Validation Enable
ROM=Y, EEPROM=N
3REF3_VALTMR_ENR/W0x0 REF3 Validation Timer Enable
ROM=Y, EEPROM=N
2REF3_PPM_ENR/W0x0 REF3 Freq ppm Enable
ROM=Y, EEPROM=N
1REF3_MISSCLK_ENR/W0x0 REF3 Missing Clock Detect Enable
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.72 R83 (Offset = 0x53)

Return to the Summary Table.

Table 1-74 R83 Field Descriptions
BitFieldTypeResetDescription
7:6REF3_DET_CLK_DIVR/W0x0 REF3 Clock Detector Divider. Bit 0 controls the divide value (0=Div4, 1=Div16). Bit 1, if set, causes the divider to be bypassed.
ROM=Y, EEPROM=N
  • 0x0 = Div By 4
  • 0x1 = Div By 16
  • 0x2 = Bypass
  • 0x3 = Bypass (Reserved)
5:4REF2_DET_CLK_DIVR/W0x0 REF2 Clock Detector Divider. Bit 0 controls the divide value (0=Div4, 1=Div16). Bit 1, if set, causes the divider to be bypassed.
ROM=Y, EEPROM=N
  • 0x0 = Div By 4
  • 0x1 = Div By 16
  • 0x2 = Bypass
  • 0x3 = Bypass (Reserved)
3:2REF1_DET_CLK_DIVR/W0x0 REF1 Clock Detector Divider. Bit 0 controls the divide value (0=Div4, 1=Div16). Bit 1, if set, causes the divider to be bypassed.
ROM=Y, EEPROM=N
  • 0x0 = Div By 4
  • 0x1 = Div By 16
  • 0x2 = Bypass
  • 0x3 = Bypass (Reserved)
1:0REF0_DET_CLK_DIVR/W0x0 REF0 Clock Detector Divider. Bit 0 controls the divide value (0=Div4, 1=Div16). Bit 1, if set, causes the divider to be bypassed.
ROM=Y, EEPROM=N
  • 0x0 = Div By 4
  • 0x1 = Div By 16
  • 0x2 = Bypass
  • 0x3 = Bypass (Reserved)

1.73 R84 (Offset = 0x54)

Return to the Summary Table.

Table 1-75 R84 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF0_MISSCLK_DIV_21:16R/W0x0 See Register 86

1.74 R85 (Offset = 0x55)

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Table 1-76 R85 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_MISSCLK_DIV_15:8R/W0x0 See Register 86

1.75 R86 (Offset = 0x56)

Return to the Summary Table.

Table 1-77 R86 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_MISSCLK_DIVR/W0x0 REF0 Missing Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF0 or VCO2/5 to REF0 (determined by REF0_MISSCLK_VCOSEL selection) with some offset added for upper bound.
ROM=Y, EEPROM=N

1.76 R87 (Offset = 0x57)

Return to the Summary Table.

Table 1-78 R87 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF1_MISSCLK_DIV_21:16R/W0x0 See Register 89

1.77 R88 (Offset = 0x58)

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Table 1-79 R88 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_MISSCLK_DIV_15:8R/W0x0 See Register 89

1.78 R89 (Offset = 0x59)

Return to the Summary Table.

Table 1-80 R89 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_MISSCLK_DIVR/W0x0 REF1 Missing Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF1 or VCO2/5 to REF0 (determined by REF1_MISSCLK_VCOSEL selection) with some offset added for upper bound.
ROM=Y, EEPROM=N

1.79 R90 (Offset = 0x5A)

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Table 1-81 R90 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF2_MISSCLK_DIV_21:16R/W0x0 See Register 92

1.80 R91 (Offset = 0x5B)

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Table 1-82 R91 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_MISSCLK_DIV_15:8R/W0x0 See Register 92

1.81 R92 (Offset = 0x5C)

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Table 1-83 R92 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_MISSCLK_DIVR/W0x0 REF2 Missing Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF2 or VCO2/5 to REF2 (determined by REF0_MISSCLK_VCOSEL selection) with some offset added for upper bound.
ROM=Y, EEPROM=N

1.82 R93 (Offset = 0x5D)

Return to the Summary Table.

Table 1-84 R93 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF3_MISSCLK_DIV_21:16R/W0x0 See Register 95

1.83 R94 (Offset = 0x5E)

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Table 1-85 R94 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_MISSCLK_DIV_15:8R/W0x0 See Register 95

1.84 R95 (Offset = 0x5F)

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Table 1-86 R95 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_MISSCLK_DIVR/W0x0 REF3 Missing Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF3 or VCO2/5 to REF3 (determined by REF0_MISSCLK_VCOSEL selection) with some offset added for upper bound.
ROM=Y, EEPROM=N

1.85 R96 (Offset = 0x60)

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Table 1-87 R96 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:1RESERVEDR0x0 Reserved
0REF0_MISSCLK_VCOSELR/W0x0 Missing/Early Clock Detector VCO selection for all references. Also selects TEC clock source.
ROM=Y, EEPROM=N
  • 0x0 = VCO3
  • 0x1 = VCO2

1.86 R97 (Offset = 0x61)

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Table 1-88 R97 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF0_EARLY_CLK_DIV_21:16R/W0x0 See Register 99

1.87 R98 (Offset = 0x62)

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Table 1-89 R98 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_EARLY_CLK_DIV_15:8R/W0x0 See Register 99

1.88 R99 (Offset = 0x63)

Return to the Summary Table.

Table 1-90 R99 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_EARLY_CLK_DIVR/W0x0 REF0 Early Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF0 or VCO2/5 to REF0 (determined by REF0_MISSCLK_VCOSEL selection) with some offset subtracted for lower bound.
ROM=Y, EEPROM=N

1.89 R100 (Offset = 0x64)

Return to the Summary Table.

Table 1-91 R100 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF1_EARLY_CLK_DIV_21:16R/W0x0 See Register 102

1.90 R101 (Offset = 0x65)

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Table 1-92 R101 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_EARLY_CLK_DIV_15:8R/W0x0 See Register 102

1.91 R102 (Offset = 0x66)

Return to the Summary Table.

Table 1-93 R102 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_EARLY_CLK_DIVR/W0x0 REF1 Early Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF1 or VCO2/5 to REF1 (determined by REF0_MISSCLK_VCOSEL selection) with some offset subtracted for lower bound.
ROM=Y, EEPROM=N

1.92 R103 (Offset = 0x67)

Return to the Summary Table.

Table 1-94 R103 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF2_EARLY_CLK_DIV_21:16R/W0x0 See Register 105

1.93 R104 (Offset = 0x68)

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Table 1-95 R104 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_EARLY_CLK_DIV_15:8R/W0x0 See Register 105

1.94 R105 (Offset = 0x69)

Return to the Summary Table.

Table 1-96 R105 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_EARLY_CLK_DIVR/W0x0 REF2 Early Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF2 or VCO2/5 to REF2 (determined by REF0_MISSCLK_VCOSEL selection) with some offset subtracted for lower bound.
ROM=Y, EEPROM=N

1.95 R106 (Offset = 0x6A)

Return to the Summary Table.

Table 1-97 R106 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF3_EARLY_CLK_DIV_21:16R/W0x0 See Register 108

1.96 R107 (Offset = 0x6B)

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Table 1-98 R107 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_EARLY_CLK_DIV_15:8R/W0x0 See Register 108

1.97 R108 (Offset = 0x6C)

Return to the Summary Table.

Table 1-99 R108 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_EARLY_CLK_DIVR/W0x0 REF3 Early Clock Detector Divider. 21-bit divide value. Should be equal to the ratio of either VCO3/2 to REF3 or VCO2/5 to REF3 (determined by REF0_MISSCLK_VCOSEL selection) with some offset subtracted for lower bound.
ROM=Y, EEPROM=N

1.98 R109 (Offset = 0x6D)

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Table 1-100 R109 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF0_PPM_MIN_14:8R/W0x0 See Register 110

1.99 R110 (Offset = 0x6E)

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Table 1-101 R110 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_PPM_MINR/W0x0 REF0 Frequency PPM Lower Limit
ROM=Y, EEPROM=N

1.100 R111 (Offset = 0x6F)

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Table 1-102 R111 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF0_PPM_MAX_14:8R/W0x0 See Register 112

1.101 R112 (Offset = 0x70)

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Table 1-103 R112 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_PPM_MAXR/W0x0 REF0 Frequency PPM Upper Limit
ROM=Y, EEPROM=N

1.102 R113 (Offset = 0x71)

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Table 1-104 R113 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF1_PPM_MIN_14:8R/W0x0 See Register 114

1.103 R114 (Offset = 0x72)

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Table 1-105 R114 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_PPM_MINR/W0x0 REF1 Frequency PPM Lower Limit
ROM=Y, EEPROM=N

1.104 R115 (Offset = 0x73)

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Table 1-106 R115 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF1_PPM_MAX_14:8R/W0x0 See Register 116

1.105 R116 (Offset = 0x74)

Return to the Summary Table.

Table 1-107 R116 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_PPM_MAXR/W0x0 REF1 Frequency PPM Upper Limit
ROM=Y, EEPROM=N

1.106 R117 (Offset = 0x75)

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Table 1-108 R117 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF2_PPM_MIN_14:8R/W0x0 See Register 118

1.107 R118 (Offset = 0x76)

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Table 1-109 R118 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_PPM_MINR/W0x0 REF2 Frequency PPM Lower Limit
ROM=Y, EEPROM=N

1.108 R119 (Offset = 0x77)

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Table 1-110 R119 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF2_PPM_MAX_14:8R/W0x0 See Register 120

1.109 R120 (Offset = 0x78)

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Table 1-111 R120 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_PPM_MAXR/W0x0 REF2 Frequency PPM Upper Limit
ROM=Y, EEPROM=N

1.110 R121 (Offset = 0x79)

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Table 1-112 R121 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF3_PPM_MIN_14:8R/W0x0 See Register 122

1.111 R122 (Offset = 0x7A)

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Table 1-113 R122 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_PPM_MINR/W0x0 REF3 Frequency PPM Lower Limit
ROM=Y, EEPROM=N

1.112 R123 (Offset = 0x7B)

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Table 1-114 R123 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0REF3_PPM_MAX_14:8R/W0x0 See Register 124

1.113 R124 (Offset = 0x7C)

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Table 1-115 R124 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_PPM_MAXR/W0x0 REF3 Frequency PPM Upper Limit
ROM=Y, EEPROM=N

1.114 R141 (Offset = 0x8D)

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Table 1-116 R141 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:4REF2_PH_VALID_CNT_MSBR/W0x0 REF2 phase detector validation. Extra 3 bits for REF2 phase detector validation counter. Lower 28-bits are in REF2_CNTSTRT. REF2 frequency PPM detect validation and phase detect validation are mutually exclusive. Only one of REF2_PPM_EN or REF2_PH_VALID_EN may be enabled at same time.
ROM=Y, EEPROM=N
3:0REF2_CNTSTRT_27:24R/W0x0 See Register 144

1.115 R142 (Offset = 0x8E)

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Table 1-117 R142 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_CNTSTRT_23:16R/W0x0 See Register 144

1.116 R143 (Offset = 0x8F)

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Table 1-118 R143 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_CNTSTRT_15:8R/W0x0 See Register 144

1.117 R144 (Offset = 0x90)

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Table 1-119 R144 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_CNTSTRTR/W0x0 28-bit REF2 PPM detect counter. REF2 decreases a counter reset by REF2_CNTSTRT value. When this becomes 0, then counter reset by REF2_HOLD_CNTSTRT is the error and used to know frequency accuracy.
ROM=Y, EEPROM=N

1.118 R145 (Offset = 0x91)

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Table 1-120 R145 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0REF2_HOLD_CNTSTRT_27:24R/W0x0 See Register 148

1.119 R146 (Offset = 0x92)

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Table 1-121 R146 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_HOLD_CNTSTRT_23:16R/W0x0 See Register 148

1.120 R147 (Offset = 0x93)

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Table 1-122 R147 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_HOLD_CNTSTRT_15:8R/W0x0 See Register 148

1.121 R148 (Offset = 0x94)

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Table 1-123 R148 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_HOLD_CNTSTRTR/W0x0 28-bit REF2 PPM detect counter. XO decreases a counter reset by REF2_HOLD_CNTSTRT. When counter reset by REF2_CNTSTRT becomes 0, this counter reset by REF2_HOLD_CNTSTRT contains the time error from which PPM error may be determined.
ROM=Y, EEPROM=N

1.122 R149 (Offset = 0x95)

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Table 1-124 R149 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:4REF3_PH_VALID_CNT_MSBR/W0x0 REF3 phase detector validation. Extra 3 bits for REF3 phase detector validation counter. Lower 28-bits are in REF3_CNTSTRT. REF3 frequency PPM detect validation and phase detect validation are mutually exclusive. Only one of REF3_PPM_EN or REF3_PH_VALID_EN may be enabled at same time.
ROM=Y, EEPROM=N
3:0REF3_CNTSTRT_27:24R/W0x0 See Register 152

1.123 R150 (Offset = 0x96)

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Table 1-125 R150 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_CNTSTRT_23:16R/W0x0 See Register 152

1.124 R151 (Offset = 0x97)

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Table 1-126 R151 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_CNTSTRT_15:8R/W0x0 See Register 152

1.125 R152 (Offset = 0x98)

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Table 1-127 R152 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_CNTSTRTR/W0x0 28-bit REF3 PPM detect counter. REF3 decreases a counter reset by REF3_CNTSTRT value. When this becomes 0, then counter reset by REF3_HOLD_CNTSTRT is the error and used to know frequency accuracy.
ROM=Y, EEPROM=N

1.126 R153 (Offset = 0x99)

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Table 1-128 R153 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0REF3_HOLD_CNTSTRT_27:24R/W0x0 See Register 156

1.127 R154 (Offset = 0x9A)

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Table 1-129 R154 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_HOLD_CNTSTRT_23:16R/W0x0 See Register 156

1.128 R155 (Offset = 0x9B)

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Table 1-130 R155 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_HOLD_CNTSTRT_15:8R/W0x0 See Register 156

1.129 R156 (Offset = 0x9C)

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Table 1-131 R156 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_HOLD_CNTSTRTR/W0x0 28-bit REF3 PPM detect counter. XO decreases a counter reset by REF3_HOLD_CNTSTRT. When counter reset by REF3_CNTSTRT becomes 0, this counter reset by REF3_HOLD_CNTSTRT contains the time error from which PPM error may be determined.
ROM=Y, EEPROM=N

1.130 R157 (Offset = 0x9D)

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Table 1-132 R157 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0REF0VLDTMRR/W0x0 REF0 Validation Timer. All selected validations must be valid for selected amount of time before the IN0/REF0 is considered valid.
ROM=Y, EEPROM=N
  • 0x0 = 0.1 ms
  • 0x1 = 0.2 ms
  • 0x2 = 0.4 ms
  • 0x3 = 0.8 ms
  • 0x4 = 1.6 ms
  • 0x5 = 3.2 ms
  • 0x6 = 6.4 ms
  • 0x7 = 12.8 ms
  • 0x8 = 25.6 ms
  • 0x9 = 51.2 ms
  • 0xA = 102.4 ms
  • 0xB = 204.8 ms
  • 0xC = 409.6 ms
  • 0xD = 819.2 ms
  • 0xE = 1.6 s
  • 0xF = 3.3 s
  • 0x10 = 6.6 s
  • 0x11 = 13.1 s
  • 0x12 = 26.2 s
  • 0x13 = 52.4 s
  • 0x14 = 1.7 min
  • 0x15 = 3.5 min
  • 0x16 = 7.0 min
  • 0x17 = 14.0 min
  • 0x18 = 28.0 min
  • 0x19 = 55.9 min
  • 0x1A = 1.9 hr
  • 0x1B = 3.7 hr
  • 0x1C = 7.5 hr
  • 0x1D = 14.9 hr
  • 0x1E = 29.8 hr
  • 0x1F = 59.7 hr

1.131 R158 (Offset = 0x9E)

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Table 1-133 R158 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0REF1VLDTMRR/W0x0 REF1 Validation Timer. All selected validations must be valid for selected amount of time before the IN1/REF1 is considered valid.
ROM=Y, EEPROM=N
  • 0x0 = 0.1 ms
  • 0x1 = 0.2 ms
  • 0x2 = 0.4 ms
  • 0x3 = 0.8 ms
  • 0x4 = 1.6 ms
  • 0x5 = 3.2 ms
  • 0x6 = 6.4 ms
  • 0x7 = 12.8 ms
  • 0x8 = 25.6 ms
  • 0x9 = 51.2 ms
  • 0xA = 102.4 ms
  • 0xB = 204.8 ms
  • 0xC = 409.6 ms
  • 0xD = 819.2 ms
  • 0xE = 1.6 s
  • 0xF = 3.3 s
  • 0x10 = 6.6 s
  • 0x11 = 13.1 s
  • 0x12 = 26.2 s
  • 0x13 = 52.4 s
  • 0x14 = 1.7 min
  • 0x15 = 3.5 min
  • 0x16 = 7.0 min
  • 0x17 = 14.0 min
  • 0x18 = 28.0 min
  • 0x19 = 55.9 min
  • 0x1A = 1.9 hr
  • 0x1B = 3.7 hr
  • 0x1C = 7.5 hr
  • 0x1D = 14.9 hr
  • 0x1E = 29.8 hr
  • 0x1F = 59.7 hr

1.132 R159 (Offset = 0x9F)

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Table 1-134 R159 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0REF2VLDTMRR/W0x0 REF2 Validation Timer. All selected validations must be valid for selected amount of time before the IN2/REF2 is considered valid.
ROM=Y, EEPROM=N
  • 0x0 = 0.1 ms
  • 0x1 = 0.2 ms
  • 0x2 = 0.4 ms
  • 0x3 = 0.8 ms
  • 0x4 = 1.6 ms
  • 0x5 = 3.2 ms
  • 0x6 = 6.4 ms
  • 0x7 = 12.8 ms
  • 0x8 = 25.6 ms
  • 0x9 = 51.2 ms
  • 0xA = 102.4 ms
  • 0xB = 204.8 ms
  • 0xC = 409.6 ms
  • 0xD = 819.2 ms
  • 0xE = 1.6 s
  • 0xF = 3.3 s
  • 0x10 = 6.6 s
  • 0x11 = 13.1 s
  • 0x12 = 26.2 s
  • 0x13 = 52.4 s
  • 0x14 = 1.7 min
  • 0x15 = 3.5 min
  • 0x16 = 7.0 min
  • 0x17 = 14.0 min
  • 0x18 = 28.0 min
  • 0x19 = 55.9 min
  • 0x1A = 1.9 hr
  • 0x1B = 3.7 hr
  • 0x1C = 7.5 hr
  • 0x1D = 14.9 hr
  • 0x1E = 29.8 hr
  • 0x1F = 59.7 hr

1.133 R160 (Offset = 0xA0)

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Table 1-135 R160 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0REF3VLDTMRR/W0x0 REF3 Validation Timer. All selected validations must be valid for selected amount of time before the IN3/REF3 is considered valid.
ROM=Y, EEPROM=N
  • 0x0 = 0.1 ms
  • 0x1 = 0.2 ms
  • 0x2 = 0.4 ms
  • 0x3 = 0.8 ms
  • 0x4 = 1.6 ms
  • 0x5 = 3.2 ms
  • 0x6 = 6.4 ms
  • 0x7 = 12.8 ms
  • 0x8 = 25.6 ms
  • 0x9 = 51.2 ms
  • 0xA = 102.4 ms
  • 0xB = 204.8 ms
  • 0xC = 409.6 ms
  • 0xD = 819.2 ms
  • 0xE = 1.6 s
  • 0xF = 3.3 s
  • 0x10 = 6.6 s
  • 0x11 = 13.1 s
  • 0x12 = 26.2 s
  • 0x13 = 52.4 s
  • 0x14 = 1.7 min
  • 0x15 = 3.5 min
  • 0x16 = 7.0 min
  • 0x17 = 14.0 min
  • 0x18 = 28.0 min
  • 0x19 = 55.9 min
  • 0x1A = 1.9 hr
  • 0x1B = 3.7 hr
  • 0x1C = 7.5 hr
  • 0x1D = 14.9 hr
  • 0x1E = 29.8 hr
  • 0x1F = 59.7 hr

1.134 R161 (Offset = 0xA1)

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Table 1-136 R161 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF0_PH_VALID_THR_13:8R/W0x0 REF0 Phase Validation Threshold
ROM=Y, EEPROM=N

1.135 R162 (Offset = 0xA2)

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Table 1-137 R162 Field Descriptions
BitFieldTypeResetDescription
7:0REF0_PH_VALID_THRR/W0x0 REF0 Phase Validation Threshold
ROM=Y, EEPROM=N

1.136 R163 (Offset = 0xA3)

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Table 1-138 R163 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF1_PH_VALID_THR_13:8R/W0x0 REF1 Phase Validation Threshold
ROM=Y, EEPROM=N

1.137 R164 (Offset = 0xA4)

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Table 1-139 R164 Field Descriptions
BitFieldTypeResetDescription
7:0REF1_PH_VALID_THRR/W0x0 REF1 Phase Validation Threshold
ROM=Y, EEPROM=N

1.138 R165 (Offset = 0xA5)

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Table 1-140 R165 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF2_PH_VALID_THR_13:8R/W0x0 REF2 Phase Validation Threshold
ROM=Y, EEPROM=N

1.139 R166 (Offset = 0xA6)

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Table 1-141 R166 Field Descriptions
BitFieldTypeResetDescription
7:0REF2_PH_VALID_THRR/W0x0 REF2 Phase Validation Threshold
ROM=Y, EEPROM=N

1.140 R167 (Offset = 0xA7)

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Table 1-142 R167 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0REF3_PH_VALID_THR_13:8R/W0x0 REF3 Phase Validation Threshold
ROM=Y, EEPROM=N

1.141 R168 (Offset = 0xA8)

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Table 1-143 R168 Field Descriptions
BitFieldTypeResetDescription
7:0REF3_PH_VALID_THRR/W0x0 REF3 Phase Validation Threshold
ROM=Y, EEPROM=N

1.142 R170 (Offset = 0xAA)

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Table 1-144 R170 Field Descriptions
BitFieldTypeResetDescription
7:0NVMSCRCR0x0 NVM Stored CRC
ROM=N, EEPROM=N

1.143 R171 (Offset = 0xAB)

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Table 1-145 R171 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6REGCOMMITR/WSC0x0 Copy fields which also exist in SRAM to SRAM memory. The REGCOMMIT bit is automatically cleared to 0 when the transfer is complete. Next an EEPROM programming operation may be performed to update NVM EEPROM. When programming to alter an NVM profile, it is suggested to toggle PD# to assure default conditions, change the desired fields, then assert the REGCOMMIT bit.
ROM=N, EEPROM=N
5NVMCRCERRR0x0 NVM CRC Error Indication. The NVMCRCERR bit is set to 1 if a CRC Error has been detected when reading back from on-chip EEPROM during device configuration.
ROM=N, EEPROM=N
4RESERVEDR0x0 Reserved
3RESERVEDR0x0 Reserved
2NVMBUSYR0x0 NVM Program Busy Indication. The NVMBUSY bit is 1 during an on-chip EEPROM Erase/Program cycle. While NVMBUSY is 1 the on-chip EEPROM cannot be accessed. Toggling PD# or removing power while NVMBUSY is asserted will corrupt the EEPROM.
ROM=N, EEPROM=N
1NVMERASER/WSC0x0 NVM Erase Start. The NVMERASE bit is used to begin an on-chip EEPROM Erase cycle. The Erase cycle is only initiated if the immediately preceding I2C/SMBus transaction was a write to the NVMUNLK register with the appropriate code. The NVMERASE bit is automatically cleared to 0.
0NVMPROGR/WSC0x0 NVM Program Start. The NVMPROG bit is used to begin an on-chip EEPROM Program cycle. The Program cycle is only initiated if the immediately preceding I2C/SMBus transaction was a write to the NVMUNLK register with the appropriate code. The NVMPROG bit is automatically cleared to 0.

1.144 R172 (Offset = 0xAC)

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Table 1-146 R172 Field Descriptions
BitFieldTypeResetDescription
7:0NVMLCRCR0x0 NVM Live CRC
ROM=N, EEPROM=N

1.145 R173 (Offset = 0xAD)

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Table 1-147 R173 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0MEMADR_12:8R/W0x0 See Register 174

1.146 R174 (Offset = 0xAE)

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Table 1-148 R174 Field Descriptions
BitFieldTypeResetDescription
7:0MEMADRR/W0x0 Memory Address. The MEMADR value determines the starting address for access to the on-chip memories. This same MEMADR value is used for EEPROM and SRAM access which share the same memory map and also ROM access.
The NVMDAT field is used to read and write from EEPROM.
The RAMDAT field is used to read and write from SRAM.
The ROMDAT field is used to read and write from ROM.

1.147 R175 (Offset = 0xAF)

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Table 1-149 R175 Field Descriptions
BitFieldTypeResetDescription
7:0NVMDATR/W0x0 EEPROM Read Data. The first time an I2C/SMBus read transaction accesses the NVMDAT register address, either because it was explicitly targeted or because the address was auto-incremented, the read transaction will returnthe EEPROM data located at the address specified by the MEMADR register. Any additional read's which are part ofthe same transaction will cause the EEPROM address to be incremented and the next EEPROM data byte will bereturned. The I2C/SMBus address will no longer be auto-incremented, i.e the I2C/SMBus address will be locked tothe NVMDAT register after the first access. Access to the NVMDAT register will terminate at the end of the currentI2C/SMBus transaction.
ROM=N, EEPROM=N

1.148 R176 (Offset = 0xB0)

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Table 1-150 R176 Field Descriptions
BitFieldTypeResetDescription
7:0RAMDATR/W0x0 RAM Read/Write Data. The first time an I2C/SMBus read or write transaction accesses the RAMDAT register address, either because it was explicitly targeted or because the address was auto-incremented, a read transaction will return the RAM data located at the address specified by the MEMADR register and a write transaction will cause the current I2C/SMBus data to be written to the address specified by the MEMADR register. Any additional accesses which are part of the same transaction will cause the RAM address to be incremented and a read or write access will take place to the next SRAM address. The I2C/SMBus address will no longer be auto-incremented (that is, the I2C/SMBus address will be locked to the RAMDAT register after the first access). Access to the RAMDAT register will terminate at the end of the current I2C/SMBus transaction.
ROM=N, EEPROM=N

1.149 R180 (Offset = 0xB4)

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Table 1-151 R180 Field Descriptions
BitFieldTypeResetDescription
7:0NVMUNLKR/W0x0 NVM Prog Unlock. The NVMUNLK register must be written immediately prior to setting the NVMERASE and NVMPROG bit, otherwise the Erase/Program cycle will not be triggered. NVMUNLK must be written with a value of 0xEA.
ROM=N, EEPROM=N

1.150 R223 (Offset = 0xDF)

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Table 1-152 R223 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL1_REF0_AUTO_PRTYR/W0x0 REF0 Priority for Automatic Switchover. Sets the priority for REF0 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL1_REF1_AUTO_PRTYR/W0x0 REF1 Priority for Automatic Switchover. Sets the priority for REF1 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.151 R224 (Offset = 0xE0)

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Table 1-153 R224 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL1_REF2_AUTO_PRTYR/W0x0 REF2 Priority for Automatic Switchover. Sets the priority for REF2 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL1_REF3_AUTO_PRTYR/W0x0 REF3 Priority for Automatic Switchover. Sets the priority for REF3 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.152 R225 (Offset = 0xE1)

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Table 1-154 R225 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL1_REF4_AUTO_PRTYR/W0x0 REF4 Priority for Automatic Switchover. Sets the priority for REF4 feedback from APLL2 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL1_REF5_AUTO_PRTYR/W0x0 REF5 Priority for Automatic Switchover. Sets the priority for REF5 feedback from APLL3 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.153 R226 (Offset = 0xE2)

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Table 1-155 R226 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5:3DPLL1_MAN_REFSELR/W0x0 DPLL1 Manual Reference Selection Mode. Determines how the manually selected reference is chosen. If this is set to a '1', the manually selected reference is taken from a GPIO input pin. If it is set to a '0', the manually selected reference is taken from
ROM=Y, EEPROM=N
  • 0x0 = REF0
  • 0x1 = REF1
  • 0x2 = REF2
  • 0x3 = REF3
  • 0x4 = PLL2
  • 0x5 = PLL3
2DPLL1_MAN_SWITCH_PIN_MODER/W0x0 DPLL1 Manual Reference Selection Mode. Determines how the manually selected reference is chosen. If this is set to a '1', the manually selected reference is taken from a GPIO input pin. If it is set to a '0', the manually selected reference is taken from a register.
ROM=Y, EEPROM=N
  • 0x0 = Register
  • 0x1 = Pin
1:0DPLL1_SWITCH_MODER/W0x0 DPLL1 Reference Switchover Mode. Selects between Automatic Non-revertive, Automatic Revertive, Manual Selection with Automatic Fallback, and Manual Selection with Automatic Holdover.
ROM=Y, EEPROM=N
  • 0x0 = Auto non-revertive
  • 0x1 = Auto revertive
  • 0x2 = Manual with fallback
  • 0x3 = Manual with holdover

1.154 R227 (Offset = 0xE3)

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Table 1-156 R227 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_REFSEL_STATR0x0 Reports the DPLL1 selected reference
ROM=N, EEPROM=N
  • 0x0 = Holdover
  • 0x1 = REF0
  • 0x2 = REF1
  • 0x4 = REF2
  • 0x8 = REF3
  • 0x10 = APLL2
  • 0x20 = APLL3

1.155 R228 (Offset = 0xE4)

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Table 1-157 R228 Field Descriptions
BitFieldTypeResetDescription
7DPLL1_LOCKDET_PPM_ENR/W0x0 DPLL frequency lock detect enable
ROM=Y, EEPROM=N
6:0DPLL1_LOCKDET_PPM_MAX_14:8R/W0x0 See Register 229

1.156 R229 (Offset = 0xE5)

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Table 1-158 R229 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_PPM_MAXR/W0x0 DPLL frequency lock detect in-lock threshold
ROM=Y, EEPROM=N

1.157 R230 (Offset = 0xE6)

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Table 1-159 R230 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0DPLL1_UNLOCKDET_PPM_MAX_14:8R/W0x0 See Register 231

1.158 R231 (Offset = 0xE7)

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Table 1-160 R231 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_UNLOCKDET_PPM_MAXR/W0x0 DPLL frequency lock detect out-of-lock threshold
ROM=Y, EEPROM=N

1.159 R232 (Offset = 0xE8)

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Table 1-161 R232 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_LOCKDET2_PPM_CNTSTRT_29:24R/W0x0 See Register 235

1.160 R233 (Offset = 0xE9)

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Table 1-162 R233 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET2_PPM_CNTSTRT_23:16R/W0x0 See Register 235

1.161 R234 (Offset = 0xEA)

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Table 1-163 R234 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET2_PPM_CNTSTRT_15:8R/W0x0 See Register 235

1.162 R235 (Offset = 0xEB)

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Table 1-164 R235 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET2_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect reference count value used with DPLL1 feedback configuration 2
ROM=Y, EEPROM=N

1.163 R236 (Offset = 0xEC)

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Table 1-165 R236 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_LOCKDET_PPM_CNTSTRT_29:24R/W0x0 See Register 239

1.164 R237 (Offset = 0xED)

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Table 1-166 R237 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_PPM_CNTSTRT_23:16R/W0x0 See Register 239

1.165 R238 (Offset = 0xEE)

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Table 1-167 R238 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_PPM_CNTSTRT_15:8R/W0x0 DPLL frequency lock detect reference count value used with DPLL1 feedback configuration 1
ROM=Y, EEPROM=N

1.166 R239 (Offset = 0xEF)

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Table 1-168 R239 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect reference count value used with DPLL1 feedback configuration 1
ROM=Y, EEPROM=N

1.167 R240 (Offset = 0xF0)

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Table 1-169 R240 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_LOCKDET_VCO_PPM_CNTSTRT_29:24R/W0x0 See Register 243

1.168 R241 (Offset = 0xF1)

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Table 1-170 R241 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_VCO_PPM_CNTSTRT_23:16R/W0x0 See Register 243

1.169 R242 (Offset = 0xF2)

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Table 1-171 R242 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_VCO_PPM_CNTSTRT_15:8R/W0x0 See Register 243

1.170 R243 (Offset = 0xF3)

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Table 1-172 R243 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LOCKDET_VCO_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect VCO count value
ROM=Y, EEPROM=N

1.171 R244 (Offset = 0xF4)

Return to the Summary Table.

Table 1-173 R244 Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0x0 Reserved
2:1RESERVEDR0x0 Reserved
0DPLL1_STATUS_PPM_LOCKR0x0 Readback lock indicator from DPLL PPM Checker
ROM=N, EEPROM=N

1.172 R247 (Offset = 0xF7)

Return to the Summary Table.

Table 1-174 R247 Field Descriptions
BitFieldTypeResetDescription
7DPLL1_LOOP_ENR/W0x0 Enable DPLL1 loop filter and R-Div mash engine
ROM=Y, EEPROM=N
6DPLL1_PHASE_CANCEL_ENR/W0x0 Enable Phase Cancellation
ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4DPLL1_PHS1_ENR/W0x0 Enable holdover exit phase slew control .
ROM=Y, EEPROM=N
3DPLL1_ZDM_ENR/W0x0 Enable Zero Delay
ROM=Y, EEPROM=N
2DPLL1_HIST_ENR/W0x0 Enable History word to be used during holdover
ROM=Y, EEPROM=N
1DPLL1_PHASE_CANCEL_ALWAYSR/W0x0 Force phase cancellation to always occur when DPLL is acquiring lock
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.173 R248 (Offset = 0xF8)

Return to the Summary Table.

Table 1-175 R248 Field Descriptions
BitFieldTypeResetDescription
7DPLL1_HOLD_SLEW_LIM_ENR/W0x0 Enable slew limiter when entering holdover. Allows slew rate control between current DPLL value before entering holdover and history value. Requires DPLL1_LOOP_EN=1.
ROM=Y, EEPROM=N
6RESERVEDR0x0 Reserved
5:3RESERVEDR0x0 Reserved
2DPLL1_CLK_DIV_SRC_SELR/W0x0 DPLL1 cannot be used without DPLL2 or DPLL3 operating. DPLL1 clock select
  • 0x0 = DPLL3
  • 0x1 = DPLL2
1:0RESERVEDR0x0 Reserved

1.174 R250 (Offset = 0xFA)

Return to the Summary Table.

Table 1-176 R250 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0DPLL1_PH_OFFSET_44:40R/W0x0 See Register 255

1.175 R251 (Offset = 0xFB)

Return to the Summary Table.

Table 1-177 R251 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_PH_OFFSET_39:32R/W0x0 See Register 255

1.176 R252 (Offset = 0xFC)

Return to the Summary Table.

Table 1-178 R252 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_PH_OFFSET_31:24R/W0x0 See Register 255

1.177 R253 (Offset = 0xFD)

Return to the Summary Table.

Table 1-179 R253 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_PH_OFFSET_23:16R/W0x0 See Register 255

1.178 R254 (Offset = 0xFE)

Return to the Summary Table.

Table 1-180 R254 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_PH_OFFSET_15:8R/W0x0 See Register 255

1.179 R255 (Offset = 0xFF)

Return to the Summary Table.

Table 1-181 R255 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_PH_OFFSETR/W0x0 Phase offset to adjust and calibrate input to output phase in ZDM. This is a 2s complement number.
ROM=Y, EEPROM=N

1.180 R256 (Offset = 0x100)

Return to the Summary Table.

Table 1-182 R256 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FREE_RUN_39:32R/W0x0 See Register 260

1.181 R257 (Offset = 0x101)

Return to the Summary Table.

Table 1-183 R257 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FREE_RUN_31:24R/W0x0 See Register 260

1.182 R258 (Offset = 0x102)

Return to the Summary Table.

Table 1-184 R258 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FREE_RUN_23:16R/W0x0 See Register 260

1.183 R259 (Offset = 0x103)

Return to the Summary Table.

Table 1-185 R259 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FREE_RUN_15:8R/W0x0 See Register 260

1.184 R260 (Offset = 0x104)

Return to the Summary Table.

Table 1-186 R260 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FREE_RUNR/W0x0 DPLL1 starting word. Also non-history holdover word. Used for APLL DCO.
ROM=Y, EEPROM=N

1.185 R261 (Offset = 0x105)

Return to the Summary Table.

Table 1-187 R261 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6DPLL1_1PPS_MODER/W0x0 Set when using 1-PPS input
ROM=Y, EEPROM=N
5DPLL1_1PPS_ENR/W0x0 Set when using 1-PPS input
ROM=Y, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.186 R290 (Offset = 0x122)

Return to the Summary Table.

Table 1-188 R290 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL1_LCK_TIMER_9:8R/W0x0 See Register 291

1.187 R291 (Offset = 0x123)

Return to the Summary Table.

Table 1-189 R291 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_LCK_TIMERR/W0x0 Minimum amount of time until DPLL1_LOPL will be deasserted after starting to lock. Timer begins once device is within valid phase lock window.
ROM=Y, EEPROM=N

1.188 R292 (Offset = 0x124)

Return to the Summary Table.

Table 1-190 R292 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL1_HIST_TIMER_9:8R/W0x0 See Register 293

1.189 R293 (Offset = 0x125)

Return to the Summary Table.

Table 1-191 R293 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_HIST_TIMERR/W0x0 Time interval between history update events.
ROM=Y, EEPROM=N

1.190 R294 (Offset = 0x126)

Return to the Summary Table.

Table 1-192 R294 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:2RESERVEDR0x0 Reserved
1:0DPLL1_HOLD_TIMER_9:8R/W0x0 See Register 295

1.191 R295 (Offset = 0x127)

Return to the Summary Table.

Table 1-193 R295 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_HOLD_TIMERR/W0x0 Rate of change to DPLL or APLL numerator during phase slew control. See DPLLx_HOLD_SLEW_STEP.
ROM=Y, EEPROM=N

1.192 R296 (Offset = 0x128)

Return to the Summary Table.

Table 1-194 R296 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL1_PHS1_TIMER_9:8R/W0x0 See Register 297

1.193 R297 (Offset = 0x129)

Return to the Summary Table.

Table 1-195 R297 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_PHS1_TIMERR/W0x0 Holdover exit phase slew control. Timer controlling update period.
ROM=Y, EEPROM=N

1.194 R302 (Offset = 0x12E)

Return to the Summary Table.

Table 1-196 R302 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0DPLL1_HIST_GAINR/W0x0 History filter gain
ROM=Y, EEPROM=N

1.195 R303 (Offset = 0x12F)

Return to the Summary Table.

Table 1-197 R303 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_PL_THRESHR/W0x0 Phase lock in-lock threshold
ROM=Y, EEPROM=N

1.196 R304 (Offset = 0x130)

Return to the Summary Table.

Table 1-198 R304 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_PL_UNLK_THRESHR/W0x0 Phase lock out-of-lock threshold
ROM=Y, EEPROM=N

1.197 R305 (Offset = 0x131)

Return to the Summary Table.

Table 1-199 R305 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_PHS1_THRESHR/W0x0 Holdover exit phase slew control. Change per timer event.
ROM=Y, EEPROM=N

1.198 R308 (Offset = 0x134)

Return to the Summary Table.

Table 1-200 R308 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_HOLD_SLEW_STEPR/W0x0 When DPLL exits holdover, rate of phase change relates to the ratio of DPLLx_HOLD_SLEW_STEP divided by DPLLx_HOLD_TIMER. DPLLx_HOLD_SLEW_STEP is applied to DPLL numerator when exiting holdover or APLL numerator when using APLL relative DCO.
ROM=Y, EEPROM=N

1.199 R310 (Offset = 0x136)

Return to the Summary Table.

Table 1-201 R310 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5DPLL1_STATUS_PLR0x0 Readback the phase lock status
ROM=N, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.200 R311 (Offset = 0x137)

Return to the Summary Table.

Table 1-202 R311 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4DPLL1_DCO_SLEW_ACTIVER0x0 Readback DCO slew status
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.201 R314 (Offset = 0x13A)

Return to the Summary Table.

Table 1-203 R314 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL1_FB_DIV_32:32R/W0x0 See Register 318

1.202 R315 (Offset = 0x13B)

Return to the Summary Table.

Table 1-204 R315 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DIV_31:24R/W0x0 See Register 318

1.203 R316 (Offset = 0x13C)

Return to the Summary Table.

Table 1-205 R316 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DIV_23:16R/W0x0 See Register 318

1.204 R317 (Offset = 0x13D)

Return to the Summary Table.

Table 1-206 R317 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DIV_15:8R/W0x0 See Register 318

1.205 R318 (Offset = 0x13E)

Return to the Summary Table.

Table 1-207 R318 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DIVR/W0x0 DPLL Feedback Divider N Value used with DPLL1 feedback configuration 1. Divide value is programmed value except when using ZDM mode with FB div, actual divide value is +1.
ROM=Y, EEPROM=N

1.206 R319 (Offset = 0x13F)

Return to the Summary Table.

Table 1-208 R319 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_39:32R/W0x0 See Register 323

1.207 R320 (Offset = 0x140)

Return to the Summary Table.

Table 1-209 R320 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_31:24R/W0x0 See Register 323

1.208 R321 (Offset = 0x141)

Return to the Summary Table.

Table 1-210 R321 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_23:16R/W0x0 See Register 323

1.209 R322 (Offset = 0x142)

Return to the Summary Table.

Table 1-211 R322 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_15:8R/W0x0 See Register 323

1.210 R323 (Offset = 0x143)

Return to the Summary Table.

Table 1-212 R323 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUMR/W0x0 DPLL Feedback Divider Numerator Value used with DPLL1 feedback configuration 1
ROM=Y, EEPROM=N

1.211 R324 (Offset = 0x144)

Return to the Summary Table.

Table 1-213 R324 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DEN_39:32R/W0x0 See Register 328

1.212 R325 (Offset = 0x145)

Return to the Summary Table.

Table 1-214 R325 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DEN_31:24R/W0x0 See Register 328

1.213 R326 (Offset = 0x146)

Return to the Summary Table.

Table 1-215 R326 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DEN_23:16R/W0x0 See Register 328

1.214 R327 (Offset = 0x147)

Return to the Summary Table.

Table 1-216 R327 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DEN_15:8R/W0x0 See Register 328

1.215 R328 (Offset = 0x148)

Return to the Summary Table.

Table 1-217 R328 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_DENR/W0x0 DPLL Feedback Divider Denominator Value used with DPLL1 feedback configuration 1
ROM=Y, EEPROM=N

1.216 R329 (Offset = 0x149)

Return to the Summary Table.

Table 1-218 R329 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL1_FB2_DIV_32:32R/W0x0 See Register 333

1.217 R330 (Offset = 0x14A)

Return to the Summary Table.

Table 1-219 R330 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DIV_31:24R/W0x0 See Register 333

1.218 R331 (Offset = 0x14B)

Return to the Summary Table.

Table 1-220 R331 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DIV_23:16R/W0x0 See Register 333

1.219 R332 (Offset = 0x14C)

Return to the Summary Table.

Table 1-221 R332 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DIV_15:8R/W0x0 See Register 333

1.220 R333 (Offset = 0x14D)

Return to the Summary Table.

Table 1-222 R333 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DIVR/W0x0 DPLL Feedback Divider N Value used with DPLL1 feedback configuration 2. Divide value is programmed value except when using ZDM mode with FB div, actual divide value is +1.
ROM=Y, EEPROM=N

1.221 R334 (Offset = 0x14E)

Return to the Summary Table.

Table 1-223 R334 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_NUM_39:32R/W0x0 See Register 338

1.222 R335 (Offset = 0x14F)

Return to the Summary Table.

Table 1-224 R335 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_NUM_31:24R/W0x0 See Register 338

1.223 R336 (Offset = 0x150)

Return to the Summary Table.

Table 1-225 R336 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_NUM_23:16R/W0x0 See Register 338

1.224 R337 (Offset = 0x151)

Return to the Summary Table.

Table 1-226 R337 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_NUM_15:8R/W0x0 See Register 338

1.225 R338 (Offset = 0x152)

Return to the Summary Table.

Table 1-227 R338 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_NUMR/W0x0 DPLL Feedback Divider Numerator Value used with DPLL1 feedback configuration 2
ROM=Y, EEPROM=N

1.226 R339 (Offset = 0x153)

Return to the Summary Table.

Table 1-228 R339 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DEN_39:32R/W0x0 See Register 343

1.227 R340 (Offset = 0x154)

Return to the Summary Table.

Table 1-229 R340 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DEN_31:24R/W0x0 See Register 343

1.228 R341 (Offset = 0x155)

Return to the Summary Table.

Table 1-230 R341 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DEN_23:16R/W0x0 See Register 343

1.229 R342 (Offset = 0x156)

Return to the Summary Table.

Table 1-231 R342 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DEN_15:8R/W0x0 See Register 343

1.230 R343 (Offset = 0x157)

Return to the Summary Table.

Table 1-232 R343 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB2_DENR/W0x0 DPLL Feedback Divider Denominator Value used with DPLL1 feedback configuration 2
ROM=Y, EEPROM=N

1.231 R344 (Offset = 0x158)

Return to the Summary Table.

Table 1-233 R344 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5DPLL1_REF5_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF3. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
4DPLL1_REF4_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF4. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
3DPLL1_REF3_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF3. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
2DPLL1_REF2_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF2. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
1DPLL1_REF1_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF1. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
0DPLL1_REF0_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF0. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2

1.232 R345 (Offset = 0x159)

Return to the Summary Table.

Table 1-234 R345 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:3RESERVEDR0x0 Reserved
2:0DPLL1_FB_MASH_ORDERR/W0x0 DPLL Feedback Divider MASH Order.
ROM=Y, EEPROM=N
  • 0x0 = Integer
  • 0x1 = 1st order
  • 0x2 = 2nd order
  • 0x3 = 3rd order
  • 0x4 = 4th order

1.233 R346 (Offset = 0x15A)

Return to the Summary Table.

Table 1-235 R346 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL1_FB_FDEV_37:32R/W0x0 See Register 350

1.234 R347 (Offset = 0x15B)

Return to the Summary Table.

Table 1-236 R347 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_FDEV_31:24R/W0x0 See Register 350

1.235 R348 (Offset = 0x15C)

Return to the Summary Table.

Table 1-237 R348 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_FDEV_23:16R/W0x0 See Register 350

1.236 R349 (Offset = 0x15D)

Return to the Summary Table.

Table 1-238 R349 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_FDEV_15:8R/W0x0 See Register 350

1.237 R350 (Offset = 0x15E)

Return to the Summary Table.

Table 1-239 R350 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_FDEVR/W0x0 DPLL Feedback Divider DCO Frequency Deviation Value
ROM=Y, EEPROM=N

1.238 R351 (Offset = 0x15F)

Return to the Summary Table.

Table 1-240 R351 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL1_FB_FDEV_UPDATER/W0x0 Increment/Decrement DPLL Feedback Numerator value with DPLL_FB_FDEV value
ROM=Y, EEPROM=N

1.239 R352 (Offset = 0x160)

Return to the Summary Table.

Table 1-241 R352 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL1_FB_FDEV_ENR/W0x0 Enable DPLL DCO mode
ROM=Y, EEPROM=N

1.240 R353 (Offset = 0x161)

Return to the Summary Table.

Table 1-242 R353 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_STAT_39:32R0x0 See Register 357

1.241 R354 (Offset = 0x162)

Return to the Summary Table.

Table 1-243 R354 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_STAT_31:24R0x0 See Register 357

1.242 R355 (Offset = 0x163)

Return to the Summary Table.

Table 1-244 R355 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_STAT_23:16R0x0 See Register 357

1.243 R356 (Offset = 0x164)

Return to the Summary Table.

Table 1-245 R356 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_STAT_15:8R0x0 See Register 357

1.244 R357 (Offset = 0x165)

Return to the Summary Table.

Table 1-246 R357 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_FB_NUM_STATR0x0 Readback DPLL Feedback Divider Numerator value as a result of DCO mode
ROM=N, EEPROM=N

1.245 R358 (Offset = 0x166)

Return to the Summary Table.

Table 1-247 R358 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3DPLL1_REF0_DBLR_ENR/W0x0 DPLL Reference 0 Doubler Enable
ROM=Y, EEPROM=N
2DPLL1_REF1_DBLR_ENR/W0x0 DPLL Reference 1 Doubler Enable
ROM=Y, EEPROM=N
1DPLL1_REF2_DBLR_ENR/W0x0 DPLL Reference 2 Doubler Enable
ROM=Y, EEPROM=N
0DPLL1_REF3_DBLR_ENR/W0x0 DPLL Reference 3 Doubler Enable
ROM=Y, EEPROM=N

1.246 R359 (Offset = 0x167)

Return to the Summary Table.

Table 1-248 R359 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF0_RDIV_15:8R/W0x0 See Register 360

1.247 R360 (Offset = 0x168)

Return to the Summary Table.

Table 1-249 R360 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF0_RDIVR/W0x0 DPLL REF0 R-divider value
ROM=Y, EEPROM=N

1.248 R361 (Offset = 0x169)

Return to the Summary Table.

Table 1-250 R361 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF1_RDIV_15:8R/W0x0 See Register 362

1.249 R362 (Offset = 0x16A)

Return to the Summary Table.

Table 1-251 R362 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF1_RDIVR/W0x0 DPLL REF1 R-divider value
ROM=Y, EEPROM=N

1.250 R363 (Offset = 0x16B)

Return to the Summary Table.

Table 1-252 R363 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF2_RDIV_15:8R/W0x0 See Register 364

1.251 R364 (Offset = 0x16C)

Return to the Summary Table.

Table 1-253 R364 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF2_RDIVR/W0x0 DPLL REF2 R-divider value
ROM=Y, EEPROM=N

1.252 R365 (Offset = 0x16D)

Return to the Summary Table.

Table 1-254 R365 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF3_RDIV_15:8R/W0x0 See Register 366

1.253 R366 (Offset = 0x16E)

Return to the Summary Table.

Table 1-255 R366 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF3_RDIVR/W0x0 DPLL REF3 R-divider value
ROM=Y, EEPROM=N

1.254 R367 (Offset = 0x16F)

Return to the Summary Table.

Table 1-256 R367 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF4_RDIV_15:8R/W0x0 See Register 368

1.255 R368 (Offset = 0x170)

Return to the Summary Table.

Table 1-257 R368 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF4_RDIVR/W0x0 DPLL REF4 R-divider value
ROM=Y, EEPROM=N

1.256 R369 (Offset = 0x171)

Return to the Summary Table.

Table 1-258 R369 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF5_RDIV_15:8R/W0x0 DPLL REF5 R-divider value. For use when DPLL1 uses output of VCO3 as a reference.
ROM=Y, EEPROM=N

1.257 R370 (Offset = 0x172)

Return to the Summary Table.

Table 1-259 R370 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL1_REF5_RDIVR/W0x0 DPLL REF5 R-divider value. For use when DPLL1 uses output of VCO3 as a reference.
ROM=Y, EEPROM=N

1.258 R373 (Offset = 0x175)

Return to the Summary Table.

Table 1-260 R373 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL2_REF0_AUTO_PRTYR/W0x0 REF0 Priority for Automatic Switchover. Sets the priority for REF0 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL2_REF1_AUTO_PRTYR/W0x0 REF1 Priority for Automatic Switchover. Sets the priority for REF1 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.259 R374 (Offset = 0x176)

Return to the Summary Table.

Table 1-261 R374 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL2_REF2_AUTO_PRTYR/W0x0 REF2 Priority for Automatic Switchover. Sets the priority for REF2 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL2_REF3_AUTO_PRTYR/W0x0 REF3 Priority for Automatic Switchover. Sets the priority for REF3 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.260 R375 (Offset = 0x177)

Return to the Summary Table.

Table 1-262 R375 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL2_REF4_AUTO_PRTYR/W0x0 REF4 Priority for Automatic Switchover. Sets the priority for REF4 feedback from APLL1 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL2_REF5_AUTO_PRTYR/W0x0 REF5 Priority for Automatic Switchover. Sets the priority for REF5 feedback from APLL3 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.261 R376 (Offset = 0x178)

Return to the Summary Table.

Table 1-263 R376 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5:3DPLL2_MAN_REFSELR/W0x0 DPLL2 Manual Reference Selection
ROM=Y, EEPROM=N
  • 0x0 = REF0
  • 0x1 = REF1
  • 0x2 = REF2
  • 0x3 = REF3
  • 0x4 = PLL1
  • 0x5 = PLL3
2DPLL2_MAN_SWITCH_PIN_MODER/W0x0 DPLL2 Manual Reference Selection Mode. Determines how the manually selected reference is chosen. If this is set to a '1', the manually selected reference is taken from a GPIO input pin. If it is set to a '0', the manually selected reference is taken from a register.
ROM=Y, EEPROM=N
  • 0x0 = Register
  • 0x1 = Pin
1:0DPLL2_SWITCH_MODER/W0x0 DPLL2 Reference Switchover Mode. Selects between Automatic Non-revertive, Automatic Revertive, Manual Selection with Automatic Fallback, and Manual Selection with Automatic Holdover.
ROM=Y, EEPROM=N
  • 0x0 = Auto non-revertive
  • 0x1 = Auto revertive
  • 0x2 = Manual with fallback
  • 0x3 = Manual with holdover

1.262 R377 (Offset = 0x179)

Return to the Summary Table.

Table 1-264 R377 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_REFSEL_STATR0x0 Reads the DPLL2 selected reference
ROM=N, EEPROM=N
  • 0x0 = Holdover
  • 0x1 = REF0
  • 0x2 = REF1
  • 0x4 = REF2
  • 0x8 = REF3
  • 0x10 = APLL1
  • 0x20 = APLL3

1.263 R378 (Offset = 0x17A)

Return to the Summary Table.

Table 1-265 R378 Field Descriptions
BitFieldTypeResetDescription
7DPLL2_LOCKDET_PPM_ENR/W0x0 DPLL frequency lock detect enable
ROM=Y, EEPROM=N
6:0DPLL2_LOCKDET_PPM_MAX_14:8R/W0x0 See Register 379

1.264 R379 (Offset = 0x17B)

Return to the Summary Table.

Table 1-266 R379 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_PPM_MAXR/W0x0 DPLL frequency lock detect in-lock threshold
ROM=Y, EEPROM=N

1.265 R380 (Offset = 0x17C)

Return to the Summary Table.

Table 1-267 R380 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0DPLL2_UNLOCKDET_PPM_MAX_14:8R/W0x0 See Register 381

1.266 R381 (Offset = 0x17D)

Return to the Summary Table.

Table 1-268 R381 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_UNLOCKDET_PPM_MAXR/W0x0 DPLL frequency lock detect out-of-lock threshold
ROM=Y, EEPROM=N

1.267 R382 (Offset = 0x17E)

Return to the Summary Table.

Table 1-269 R382 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_LOCKDET2_PPM_CNTSTRT_29:24R/W0x0 See Register 385

1.268 R383 (Offset = 0x17F)

Return to the Summary Table.

Table 1-270 R383 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET2_PPM_CNTSTRT_23:16R/W0x0 See Register 385

1.269 R384 (Offset = 0x180)

Return to the Summary Table.

Table 1-271 R384 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET2_PPM_CNTSTRT_15:8R/W0x0 See Register 385

1.270 R385 (Offset = 0x181)

Return to the Summary Table.

Table 1-272 R385 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET2_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect reference count value used with DPLL2 feedback configuration 2
ROM=Y, EEPROM=N

1.271 R386 (Offset = 0x182)

Return to the Summary Table.

Table 1-273 R386 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_LOCKDET_PPM_CNTSTRT_29:24R/W0x0 See Register 389

1.272 R387 (Offset = 0x183)

Return to the Summary Table.

Table 1-274 R387 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_PPM_CNTSTRT_23:16R/W0x0 See Register 389

1.273 R388 (Offset = 0x184)

Return to the Summary Table.

Table 1-275 R388 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_PPM_CNTSTRT_15:8R/W0x0 See Register 389

1.274 R389 (Offset = 0x185)

Return to the Summary Table.

Table 1-276 R389 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect reference count value used with DPLL2 feedback configuration 1
ROM=Y, EEPROM=N

1.275 R390 (Offset = 0x186)

Return to the Summary Table.

Table 1-277 R390 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_LOCKDET_VCO_PPM_CNTSTRT_29:24R/W0x0 See Register 393

1.276 R391 (Offset = 0x187)

Return to the Summary Table.

Table 1-278 R391 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_VCO_PPM_CNTSTRT_23:16R/W0x0 See Register 393

1.277 R392 (Offset = 0x188)

Return to the Summary Table.

Table 1-279 R392 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_VCO_PPM_CNTSTRT_15:8R/W0x0 See Register 393

1.278 R393 (Offset = 0x189)

Return to the Summary Table.

Table 1-280 R393 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LOCKDET_VCO_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect VCO count value
ROM=Y, EEPROM=N

1.279 R394 (Offset = 0x18A)

Return to the Summary Table.

Table 1-281 R394 Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0x0 Reserved
2:1RESERVEDR0x0 Reserved
0DPLL2_STATUS_PPM_LOCKR0x0 Readback lock indicator from DPLL PPM Checker
ROM=N, EEPROM=N

1.280 R397 (Offset = 0x18D)

Return to the Summary Table.

Table 1-282 R397 Field Descriptions
BitFieldTypeResetDescription
7DPLL2_LOOP_ENR/W0x0 Enable DPLL2 loop filter and R-Div mash engine
ROM=Y, EEPROM=N
6DPLL2_PHASE_CANCEL_ENR/W0x0 Enable Phase Cancellation
ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4DPLL2_PHS1_ENR/W0x0 Enable holdover exit phase slew control .
ROM=Y, EEPROM=N
3DPLL2_ZDM_ENR/W0x0 Enable Zero Delay
ROM=Y, EEPROM=N
2DPLL2_HIST_ENR/W0x0 Enable History word to be used during holdover
ROM=Y, EEPROM=N
1DPLL2_PHASE_CANCEL_ALWAYSR/W0x0 Force phase cancellation to always occur when DPLL is acquiring lock
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.281 R398 (Offset = 0x18E)

Return to the Summary Table.

Table 1-283 R398 Field Descriptions
BitFieldTypeResetDescription
7DPLL2_HOLD_SLEW_LIM_ENR/W0x0 Enable slew limiter when entering holdover
ROM=Y, EEPROM=N
6:0RESERVEDR0x0 Reserved

1.282 R400 (Offset = 0x190)

Return to the Summary Table.

Table 1-284 R400 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0DPLL2_PH_OFFSET_44:40R/W0x0 See Register 405

1.283 R401 (Offset = 0x191)

Return to the Summary Table.

Table 1-285 R401 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_PH_OFFSET_39:32R/W0x0 See Register 405

1.284 R402 (Offset = 0x192)

Return to the Summary Table.

Table 1-286 R402 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_PH_OFFSET_31:24R/W0x0 See Register 405

1.285 R403 (Offset = 0x193)

Return to the Summary Table.

Table 1-287 R403 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_PH_OFFSET_23:16R/W0x0 See Register 405

1.286 R404 (Offset = 0x194)

Return to the Summary Table.

Table 1-288 R404 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_PH_OFFSET_15:8R/W0x0 See Register 405

1.287 R405 (Offset = 0x195)

Return to the Summary Table.

Table 1-289 R405 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_PH_OFFSETR/W0x0 Phase offset to adjust and calibrate input to output phase in ZDM. This is a 2s complement number.
ROM=Y, EEPROM=N

1.288 R406 (Offset = 0x196)

Return to the Summary Table.

Table 1-290 R406 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FREE_RUN_39:32R/W0x0 See Register 410

1.289 R407 (Offset = 0x197)

Return to the Summary Table.

Table 1-291 R407 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FREE_RUN_31:24R/W0x0 See Register 410

1.290 R408 (Offset = 0x198)

Return to the Summary Table.

Table 1-292 R408 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FREE_RUN_23:16R/W0x0 See Register 410

1.291 R409 (Offset = 0x199)

Return to the Summary Table.

Table 1-293 R409 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FREE_RUN_15:8R/W0x0 See Register 410

1.292 R410 (Offset = 0x19A)

Return to the Summary Table.

Table 1-294 R410 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FREE_RUNR/W0x0 DPLL2 starting word. Also non-history holdover word.
ROM=Y, EEPROM=N

1.293 R411 (Offset = 0x19B)

Return to the Summary Table.

Table 1-295 R411 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6DPLL2_1PPS_MODER/W0x0 Set when using 1-PPS input
ROM=Y, EEPROM=N
5DPLL2_1PPS_ENR/W0x0 Set when using 1-PPS input
ROM=Y, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.294 R440 (Offset = 0x1B8)

Return to the Summary Table.

Table 1-296 R440 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL2_LCK_TIMER_9:8R/W0x0 See Register 441

1.295 R441 (Offset = 0x1B9)

Return to the Summary Table.

Table 1-297 R441 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_LCK_TIMERR/W0x0 Minimum amount of time until DPLL2_LOPL will be deasserted after starting to lock. Timer begins once device is within valid phase lock window.
ROM=Y, EEPROM=N

1.296 R442 (Offset = 0x1BA)

Return to the Summary Table.

Table 1-298 R442 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL2_HIST_TIMER_9:8R/W0x0 See Register 443

1.297 R443 (Offset = 0x1BB)

Return to the Summary Table.

Table 1-299 R443 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_HIST_TIMERR/W0x0 Time interval between history update events.
ROM=Y, EEPROM=N

1.298 R444 (Offset = 0x1BC)

Return to the Summary Table.

Table 1-300 R444 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:2RESERVEDR0x0 Reserved
1:0DPLL2_HOLD_TIMER_9:8R/W0x0 See Register 445

1.299 R445 (Offset = 0x1BD)

Return to the Summary Table.

Table 1-301 R445 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_HOLD_TIMERR/W0x0 Rate of change to DPLL or APLL numerator during phase slew control. See DPLLx_HOLD_SLEW_STEP.
ROM=Y, EEPROM=N

1.300 R446 (Offset = 0x1BE)

Return to the Summary Table.

Table 1-302 R446 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL2_PHS1_TIMER_9:8R/W0x0 See Register 447

1.301 R447 (Offset = 0x1BF)

Return to the Summary Table.

Table 1-303 R447 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_PHS1_TIMERR/W0x0 Holdover exit phase slew control. Timer controlling update period.
ROM=Y, EEPROM=N

1.302 R452 (Offset = 0x1C4)

Return to the Summary Table.

Table 1-304 R452 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0DPLL2_HIST_GAINR/W0x0 History filter gain
ROM=Y, EEPROM=N

1.303 R453 (Offset = 0x1C5)

Return to the Summary Table.

Table 1-305 R453 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_PL_THRESHR/W0x0 Phase lock in-lock threshold
ROM=Y, EEPROM=N

1.304 R454 (Offset = 0x1C6)

Return to the Summary Table.

Table 1-306 R454 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_PL_UNLK_THRESHR/W0x0 Phase lock out-of-lock threshold
ROM=Y, EEPROM=N

1.305 R455 (Offset = 0x1C7)

Return to the Summary Table.

Table 1-307 R455 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_PHS1_THRESHR/W0x0 Holdover exit phase slew control. Change per timer event.
ROM=Y, EEPROM=N

1.306 R458 (Offset = 0x1CA)

Return to the Summary Table.

Table 1-308 R458 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_HOLD_SLEW_STEPR/W0x0 When DPLL exits holdover, rate of phase change relates to DPLLx_HOLD_SLEW_STEP over DPLLx_HOLD_TIMER. DPLLx_HOLD_SLEW_STEP is applied to DPLL numerator when exiting holdover or APLL numerator when using APLL relative DCO.
ROM=Y, EEPROM=N

1.307 R460 (Offset = 0x1CC)

Return to the Summary Table.

Table 1-309 R460 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5DPLL2_STATUS_PLR0x0 Readback the phase lock status
ROM=N, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.308 R461 (Offset = 0x1CD)

Return to the Summary Table.

Table 1-310 R461 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4DPLL2_DCO_SLEW_ACTIVER0x0 Readback DCO slew status
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.309 R464 (Offset = 0x1D0)

Return to the Summary Table.

Table 1-311 R464 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL2_FB_DIV_32:32R/W0x0 See Register 468

1.310 R465 (Offset = 0x1D1)

Return to the Summary Table.

Table 1-312 R465 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DIV_31:24R/W0x0 See Register 468

1.311 R466 (Offset = 0x1D2)

Return to the Summary Table.

Table 1-313 R466 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DIV_23:16R/W0x0 See Register 468

1.312 R467 (Offset = 0x1D3)

Return to the Summary Table.

Table 1-314 R467 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DIV_15:8R/W0x0 See Register 468

1.313 R468 (Offset = 0x1D4)

Return to the Summary Table.

Table 1-315 R468 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DIVR/W0x0 DPLL Feedback Divider N Value used with DPLL2 feedback configuration 1. Divide value is programmed value except when using ZDM mode with FB div, actual divide value is +1.
ROM=Y, EEPROM=N

1.314 R469 (Offset = 0x1D5)

Return to the Summary Table.

Table 1-316 R469 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_39:32R/W0x0 See Register 473

1.315 R470 (Offset = 0x1D6)

Return to the Summary Table.

Table 1-317 R470 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_31:24R/W0x0 See Register 473

1.316 R471 (Offset = 0x1D7)

Return to the Summary Table.

Table 1-318 R471 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_23:16R/W0x0 See Register 473

1.317 R472 (Offset = 0x1D8)

Return to the Summary Table.

Table 1-319 R472 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_15:8R/W0x0 See Register 473

1.318 R473 (Offset = 0x1D9)

Return to the Summary Table.

Table 1-320 R473 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUMR/W0x0 DPLL Feedback Divider Numerator Value used with DPLL2 feedback configuration 1
ROM=Y, EEPROM=N

1.319 R474 (Offset = 0x1DA)

Return to the Summary Table.

Table 1-321 R474 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DEN_39:32R/W0x0 See Register 478

1.320 R475 (Offset = 0x1DB)

Return to the Summary Table.

Table 1-322 R475 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DEN_31:24R/W0x0 See Register 478

1.321 R476 (Offset = 0x1DC)

Return to the Summary Table.

Table 1-323 R476 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DEN_23:16R/W0x0 See Register 478

1.322 R477 (Offset = 0x1DD)

Return to the Summary Table.

Table 1-324 R477 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DEN_15:8R/W0x0 See Register 478

1.323 R478 (Offset = 0x1DE)

Return to the Summary Table.

Table 1-325 R478 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_DENR/W0x0 DPLL Feedback Divider Denominator Value used with DPLL2 feedback configuration 1
ROM=Y, EEPROM=N

1.324 R479 (Offset = 0x1DF)

Return to the Summary Table.

Table 1-326 R479 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL2_FB2_DIV_32:32R/W0x0 See Register 483

1.325 R480 (Offset = 0x1E0)

Return to the Summary Table.

Table 1-327 R480 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DIV_31:24R/W0x0 See Register 483

1.326 R481 (Offset = 0x1E1)

Return to the Summary Table.

Table 1-328 R481 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DIV_23:16R/W0x0 See Register 483

1.327 R482 (Offset = 0x1E2)

Return to the Summary Table.

Table 1-329 R482 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DIV_15:8R/W0x0 See Register 483

1.328 R483 (Offset = 0x1E3)

Return to the Summary Table.

Table 1-330 R483 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DIVR/W0x0 DPLL Feedback Divider N Value used with DPLL2 feedback configuration 2. Divide value is programmed value except when using ZDM mode with FB div, actual divide value is +1.
ROM=Y, EEPROM=N

1.329 R484 (Offset = 0x1E4)

Return to the Summary Table.

Table 1-331 R484 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_NUM_39:32R/W0x0 See Register 488

1.330 R485 (Offset = 0x1E5)

Return to the Summary Table.

Table 1-332 R485 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_NUM_31:24R/W0x0 See Register 488

1.331 R486 (Offset = 0x1E6)

Return to the Summary Table.

Table 1-333 R486 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_NUM_23:16R/W0x0 See Register 488

1.332 R487 (Offset = 0x1E7)

Return to the Summary Table.

Table 1-334 R487 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_NUM_15:8R/W0x0 See Register 488

1.333 R488 (Offset = 0x1E8)

Return to the Summary Table.

Table 1-335 R488 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_NUMR/W0x0 DPLL Feedback Divider Numerator Value used with DPLL2 feedback configuration 2
ROM=Y, EEPROM=N

1.334 R489 (Offset = 0x1E9)

Return to the Summary Table.

Table 1-336 R489 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DEN_39:32R/W0x0 See Register 493

1.335 R490 (Offset = 0x1EA)

Return to the Summary Table.

Table 1-337 R490 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DEN_31:24R/W0x0 See Register 493

1.336 R491 (Offset = 0x1EB)

Return to the Summary Table.

Table 1-338 R491 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DEN_23:16R/W0x0 See Register 493

1.337 R492 (Offset = 0x1EC)

Return to the Summary Table.

Table 1-339 R492 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DEN_15:8R/W0x0 See Register 493

1.338 R493 (Offset = 0x1ED)

Return to the Summary Table.

Table 1-340 R493 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB2_DENR/W0x0 DPLL Feedback Divider Denominator Value used with DPLL2 feedback configuration 2
ROM=Y, EEPROM=N

1.339 R494 (Offset = 0x1EE)

Return to the Summary Table.

Table 1-341 R494 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5DPLL2_REF5_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF3. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
4DPLL2_REF4_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF4. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
3DPLL2_REF3_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF3. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
2DPLL2_REF2_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF2. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
1DPLL2_REF1_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF1. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
0DPLL2_REF0_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF0. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2

1.340 R495 (Offset = 0x1EF)

Return to the Summary Table.

Table 1-342 R495 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:3RESERVEDR0x0 Reserved
2:0DPLL2_FB_MASH_ORDERR/W0x0 DPLL Feedback Divider MASH Order.
ROM=Y, EEPROM=N
  • 0x0 = Integer
  • 0x1 = 1st order
  • 0x2 = 2nd order
  • 0x3 = 3rd order
  • 0x4 = 4th order

1.341 R496 (Offset = 0x1F0)

Return to the Summary Table.

Table 1-343 R496 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL2_FB_FDEV_37:32R/W0x0 See Register 500

1.342 R497 (Offset = 0x1F1)

Return to the Summary Table.

Table 1-344 R497 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_FDEV_31:24R/W0x0 See Register 500

1.343 R498 (Offset = 0x1F2)

Return to the Summary Table.

Table 1-345 R498 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_FDEV_23:16R/W0x0 See Register 500

1.344 R499 (Offset = 0x1F3)

Return to the Summary Table.

Table 1-346 R499 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_FDEV_15:8R/W0x0 See Register 500

1.345 R500 (Offset = 0x1F4)

Return to the Summary Table.

Table 1-347 R500 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_FDEVR/W0x0 DPLL Feedback Divider DCO Frequency Deviation Value
ROM=Y, EEPROM=N

1.346 R501 (Offset = 0x1F5)

Return to the Summary Table.

Table 1-348 R501 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL2_FB_FDEV_UPDATER/W0x0 Increment/Decrement DPLL Feedback Numerator value with DPLL_FB_FDEV value
ROM=Y, EEPROM=N

1.347 R502 (Offset = 0x1F6)

Return to the Summary Table.

Table 1-349 R502 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL2_FB_FDEV_ENR/W0x0 Enable DPLL DCO mode
ROM=Y, EEPROM=N

1.348 R503 (Offset = 0x1F7)

Return to the Summary Table.

Table 1-350 R503 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_STAT_39:32R0x0 See Register 507

1.349 R504 (Offset = 0x1F8)

Return to the Summary Table.

Table 1-351 R504 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_STAT_31:24R0x0 See Register 507

1.350 R505 (Offset = 0x1F9)

Return to the Summary Table.

Table 1-352 R505 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_STAT_23:16R0x0 See Register 507

1.351 R506 (Offset = 0x1FA)

Return to the Summary Table.

Table 1-353 R506 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_STAT_15:8R0x0 See Register 507

1.352 R507 (Offset = 0x1FB)

Return to the Summary Table.

Table 1-354 R507 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_FB_NUM_STATR0x0 Readback DPLL Feedback Divider Numerator value as a result of DCO mode
ROM=N, EEPROM=N

1.353 R508 (Offset = 0x1FC)

Return to the Summary Table.

Table 1-355 R508 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3DPLL2_REF0_DBLR_ENR/W0x0 DPLL Reference 0 Doubler Enable
ROM=Y, EEPROM=N
2DPLL2_REF1_DBLR_ENR/W0x0 DPLL Reference 1 Doubler Enable
ROM=Y, EEPROM=N
1DPLL2_REF2_DBLR_ENR/W0x0 DPLL Reference 2 Doubler Enable
ROM=Y, EEPROM=N
0DPLL2_REF3_DBLR_ENR/W0x0 DPLL Reference 3 Doubler Enable
ROM=Y, EEPROM=N

1.354 R509 (Offset = 0x1FD)

Return to the Summary Table.

Table 1-356 R509 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF0_RDIV_15:8R/W0x0 See Register 510

1.355 R510 (Offset = 0x1FE)

Return to the Summary Table.

Table 1-357 R510 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF0_RDIVR/W0x0 DPLL Reference 0 R divider value
ROM=Y, EEPROM=N

1.356 R511 (Offset = 0x1FF)

Return to the Summary Table.

Table 1-358 R511 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF1_RDIV_15:8R/W0x0 See Register 512

1.357 R512 (Offset = 0x200)

Return to the Summary Table.

Table 1-359 R512 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF1_RDIVR/W0x0 DPLL Reference 1 R divider value
ROM=Y, EEPROM=N

1.358 R513 (Offset = 0x201)

Return to the Summary Table.

Table 1-360 R513 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF2_RDIV_15:8R/W0x0 See Register 514

1.359 R514 (Offset = 0x202)

Return to the Summary Table.

Table 1-361 R514 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF2_RDIVR/W0x0 DPLL Reference 2 R divider value
ROM=Y, EEPROM=N

1.360 R515 (Offset = 0x203)

Return to the Summary Table.

Table 1-362 R515 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF3_RDIV_15:8R/W0x0 See Register 516

1.361 R516 (Offset = 0x204)

Return to the Summary Table.

Table 1-363 R516 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF3_RDIVR/W0x0 DPLL Reference 3 R divider value
ROM=Y, EEPROM=N

1.362 R517 (Offset = 0x205)

Return to the Summary Table.

Table 1-364 R517 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF4_RDIV_15:8R/W0x0 See Register 518

1.363 R518 (Offset = 0x206)

Return to the Summary Table.

Table 1-365 R518 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF4_RDIVR/W0x0 DPLL REF4 R-divider value
ROM=Y, EEPROM=N

1.364 R519 (Offset = 0x207)

Return to the Summary Table.

Table 1-366 R519 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF5_RDIV_15:8R/W0x0 See Register 520

1.365 R520 (Offset = 0x208)

Return to the Summary Table.

Table 1-367 R520 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL2_REF5_RDIVR/W0x0 DPLL Reference 3 R divider value
ROM=Y, EEPROM=N

1.366 R523 (Offset = 0x20B)

Return to the Summary Table.

Table 1-368 R523 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL3_REF0_AUTO_PRTYR/W0x0 REF0 Priority for Automatic Switchover. Sets the priority for REF0 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL3_REF1_AUTO_PRTYR/W0x0 REF1 Priority for Automatic Switchover. Sets the priority for REF1 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.367 R524 (Offset = 0x20C)

Return to the Summary Table.

Table 1-369 R524 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL3_REF2_AUTO_PRTYR/W0x0 REF2 Priority for Automatic Switchover. Sets the priority for REF2 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL3_REF3_AUTO_PRTYR/W0x0 REF3 Priority for Automatic Switchover. Sets the priority for REF3 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.368 R525 (Offset = 0x20D)

Return to the Summary Table.

Table 1-370 R525 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3DPLL3_REF4_AUTO_PRTYR/W0x0 REF4 Priority for Automatic Switchover. Sets the priority for REF4 feedback from APLL1 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th
2:0DPLL3_REF5_AUTO_PRTYR/W0x0 REF5 Priority for Automatic Switchover. Sets the priority for REF5 feedback from APLL2 used in Automatic Non-Revertive, Automatic Revertive, and Manual Selection with Automatic Fallback switchover modes.
ROM=Y, EEPROM=N
  • 0x0 = Not available for selection
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
  • 0x4 = 4th
  • 0x5 = 5th
  • 0x6 = 6th
  • 0x7 = 7th

1.369 R526 (Offset = 0x20E)

Return to the Summary Table.

Table 1-371 R526 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5:3DPLL3_MAN_REFSELR/W0x0 DPLL3 Manual Reference Selection Mode. Determines how the manually selected reference is chosen. If this is set to a '1', the manually selected reference is taken from a GPIO input pin. If it is set to a '0', the manually selected reference is taken from a register.
ROM=Y, EEPROM=N
  • 0x0 = REF0
  • 0x1 = REF1
  • 0x2 = REF2
  • 0x3 = REF3
  • 0x4 = PLL1
  • 0x5 = PLL2
2DPLL3_MAN_SWITCH_PIN_MODER/W0x0 DPLL3 Manual Reference Selection Mode. Determines how the manually selected reference is chosen. If this is set to a '1', the manually selected reference is taken from a GPIO input pin. If it is set to a '0', the manually selected reference is taken from a register.
ROM=Y, EEPROM=N
  • 0x0 = Register
  • 0x1 = Pin
1:0DPLL3_SWITCH_MODER/W0x0 DPLL3 Reference Switchover Mode. Selects between Automatic Non-revertive, Automatic Revertive, Manual Selection with Automatic Fallback, and Manual Selection with Automatic Holdover.
ROM=Y, EEPROM=N
  • 0x0 = Auto non-revertive
  • 0x1 = Auto revertive
  • 0x2 = Manual with fallback
  • 0x3 = Manual with holdover

1.370 R527 (Offset = 0x20F)

Return to the Summary Table.

Table 1-372 R527 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_REFSEL_STATR0x0 Reads the DPLL3 selected reference
ROM=N, EEPROM=N
  • 0x0 = Holdover
  • 0x1 = REF0
  • 0x2 = REF1
  • 0x4 = REF2
  • 0x8 = REF3
  • 0x10 = APLL1
  • 0x20 = APLL2

1.371 R528 (Offset = 0x210)

Return to the Summary Table.

Table 1-373 R528 Field Descriptions
BitFieldTypeResetDescription
7DPLL3_LOCKDET_PPM_ENR/W0x0 DPLL frequency lock detect enable
ROM=Y, EEPROM=N
6:0DPLL3_LOCKDET_PPM_MAX_14:8R/W0x0 See Register 529

1.372 R529 (Offset = 0x211)

Return to the Summary Table.

Table 1-374 R529 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_PPM_MAXR/W0x0 DPLL frequency lock detect in-lock threshold
ROM=Y, EEPROM=N

1.373 R530 (Offset = 0x212)

Return to the Summary Table.

Table 1-375 R530 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0DPLL3_UNLOCKDET_PPM_MAX_14:8R/W0x0 See Register 531

1.374 R531 (Offset = 0x213)

Return to the Summary Table.

Table 1-376 R531 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_UNLOCKDET_PPM_MAXR/W0x0 DPLL frequency lock detect out-of-lock threshold
ROM=Y, EEPROM=N

1.375 R532 (Offset = 0x214)

Return to the Summary Table.

Table 1-377 R532 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_LOCKDET2_PPM_CNTSTRT_29:24R/W0x0 See Register 535

1.376 R533 (Offset = 0x215)

Return to the Summary Table.

Table 1-378 R533 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET2_PPM_CNTSTRT_23:16R/W0x0 See Register 535

1.377 R534 (Offset = 0x216)

Return to the Summary Table.

Table 1-379 R534 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET2_PPM_CNTSTRT_15:8R/W0x0 See Register 535

1.378 R535 (Offset = 0x217)

Return to the Summary Table.

Table 1-380 R535 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET2_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect reference count value used with DPLL1 feedback configuration 2
ROM=Y, EEPROM=N

1.379 R536 (Offset = 0x218)

Return to the Summary Table.

Table 1-381 R536 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_LOCKDET_PPM_CNTSTRT_29:24R/W0x0 See Register 539

1.380 R537 (Offset = 0x219)

Return to the Summary Table.

Table 1-382 R537 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_PPM_CNTSTRT_23:16R/W0x0 See Register 539

1.381 R538 (Offset = 0x21A)

Return to the Summary Table.

Table 1-383 R538 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_PPM_CNTSTRT_15:8R/W0x0 See Register 539

1.382 R539 (Offset = 0x21B)

Return to the Summary Table.

Table 1-384 R539 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect reference count value used with DPLL3 feedback configuration 1
ROM=Y, EEPROM=N

1.383 R540 (Offset = 0x21C)

Return to the Summary Table.

Table 1-385 R540 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_LOCKDET_VCO_PPM_CNTSTRT_29:24R/W0x0 See Register 543

1.384 R541 (Offset = 0x21D)

Return to the Summary Table.

Table 1-386 R541 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_VCO_PPM_CNTSTRT_23:16R/W0x0 See Register 543

1.385 R542 (Offset = 0x21E)

Return to the Summary Table.

Table 1-387 R542 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_VCO_PPM_CNTSTRT_15:8R/W0x0 See Register 543

1.386 R543 (Offset = 0x21F)

Return to the Summary Table.

Table 1-388 R543 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LOCKDET_VCO_PPM_CNTSTRTR/W0x0 DPLL frequency lock detect VCO count value
ROM=Y, EEPROM=N

1.387 R544 (Offset = 0x220)

Return to the Summary Table.

Table 1-389 R544 Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0x0 Reserved
2:1RESERVEDR0x0 Reserved
0DPLL3_STATUS_PPM_LOCKR0x0 Readback lock indicator from DPLL PPM Checker
ROM=N, EEPROM=N

1.388 R547 (Offset = 0x223)

Return to the Summary Table.

Table 1-390 R547 Field Descriptions
BitFieldTypeResetDescription
7DPLL3_LOOP_ENR/W0x0 Enable DPLL3 loop filter and R-Div mash engine
ROM=Y, EEPROM=N
6DPLL3_PHASE_CANCEL_ENR/W0x0 Enable Phase Cancellation
ROM=Y, EEPROM=N
5DPLL3_FASTLOCK_ALWAYSR/W0x0 Always perform fastlock
ROM=Y, EEPROM=N
4DPLL3_PHS1_ENR/W0x0 Enable holdover exit phase slew control .
ROM=Y, EEPROM=N
3DPLL3_ZDM_ENR/W0x0 Enable Zero Delay mode
ROM=Y, EEPROM=N
2DPLL3_HIST_ENR/W0x0 Enable History word to be used during holdover
ROM=Y, EEPROM=N
1DPLL3_PHASE_CANCEL_ALWAYSR/W0x0 Force phase cancellation to always occur when DPLL is acquiring lock.
ROM=Y, EEPROM=N
0RESERVEDR0x0 Reserved

1.389 R548 (Offset = 0x224)

Return to the Summary Table.

Table 1-391 R548 Field Descriptions
BitFieldTypeResetDescription
7DPLL3_HOLD_SLEW_LIM_ENR/W0x0 During holdover enable slew limiter
ROM=Y, EEPROM=N
6:0RESERVEDR0x0 Reserved

1.390 R550 (Offset = 0x226)

Return to the Summary Table.

Table 1-392 R550 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0DPLL3_PH_OFFSET_44:40R/W0x0 See Register 555

1.391 R551 (Offset = 0x227)

Return to the Summary Table.

Table 1-393 R551 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_PH_OFFSET_39:32R/W0x0 See Register 555

1.392 R552 (Offset = 0x228)

Return to the Summary Table.

Table 1-394 R552 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_PH_OFFSET_31:24R/W0x0 See Register 555

1.393 R553 (Offset = 0x229)

Return to the Summary Table.

Table 1-395 R553 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_PH_OFFSET_23:16R/W0x0 See Register 555

1.394 R554 (Offset = 0x22A)

Return to the Summary Table.

Table 1-396 R554 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_PH_OFFSET_15:8R/W0x0 See Register 555

1.395 R555 (Offset = 0x22B)

Return to the Summary Table.

Table 1-397 R555 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_PH_OFFSETR/W0x0 Phase offset to adjust and calibrate input to output phase in ZDM. This is a 2s complement number.
ROM=Y, EEPROM=N

1.396 R556 (Offset = 0x22C)

Return to the Summary Table.

Table 1-398 R556 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FREE_RUN_39:32R/W0x0 See Register 560

1.397 R557 (Offset = 0x22D)

Return to the Summary Table.

Table 1-399 R557 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FREE_RUN_31:24R/W0x0 See Register 560

1.398 R558 (Offset = 0x22E)

Return to the Summary Table.

Table 1-400 R558 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FREE_RUN_23:16R/W0x0 See Register 560

1.399 R559 (Offset = 0x22F)

Return to the Summary Table.

Table 1-401 R559 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FREE_RUN_15:8R/W0x0 See Register 560

1.400 R560 (Offset = 0x230)

Return to the Summary Table.

Table 1-402 R560 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FREE_RUNR/W0x0 DPLL starting word. Also non-history holdover word.
ROM=Y, EEPROM=N

1.401 R561 (Offset = 0x231)

Return to the Summary Table.

Table 1-403 R561 Field Descriptions
BitFieldTypeResetDescription
7DPLL3_PPM_REF_SELR/W0x0 PPM Detector Reference Selection for DPLL3 LOFL. When set to 0, the selected DPLL input reference is used resulting in DPLL3 LOFL as expected. When set to 1, the XO is used as a frequency enabling LOFL for APLL3, no DPLL is required. This bit enables a "BAW LOCK" indicator.
ROM=Y, EEPROM=N
  • 0x0 = LOFL_DPLL3 = DPLL3 DLD
  • 0x1 = LOFL_DPLL3 = APLL3 DLD
6DPLL3_1PPS_MODER/W0x0 Set when using 1-PPS input
ROM=Y, EEPROM=N
5DPLL3_1PPS_ENR/W0x0 Set when using 1-PPS input
ROM=Y, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.402 R590 (Offset = 0x24E)

Return to the Summary Table.

Table 1-404 R590 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL3_LCK_TIMER_9:8R/W0x0 See Register 591

1.403 R591 (Offset = 0x24F)

Return to the Summary Table.

Table 1-405 R591 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_LCK_TIMERR/W0x0 Minimum amount of time until DPLL3_LOPL will be deasserted after starting to lock. Timer begins once device is within valid phase lock window.
ROM=Y, EEPROM=N

1.404 R592 (Offset = 0x250)

Return to the Summary Table.

Table 1-406 R592 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL3_HIST_TIMER_9:8R/W0x0 See Register 593

1.405 R593 (Offset = 0x251)

Return to the Summary Table.

Table 1-407 R593 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_HIST_TIMERR/W0x0 History timer
ROM=Y, EEPROM=N

1.406 R594 (Offset = 0x252)

Return to the Summary Table.

Table 1-408 R594 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:2RESERVEDR0x0 Reserved
1:0DPLL3_HOLD_TIMER_9:8R/W0x0 See Register 595

1.407 R595 (Offset = 0x253)

Return to the Summary Table.

Table 1-409 R595 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_HOLD_TIMERR/W0x0 Rate of change to DPLL or APLL numerator during phase slew control. See DPLLx_HOLD_SLEW_STEP.
ROM=Y, EEPROM=N

1.408 R596 (Offset = 0x254)

Return to the Summary Table.

Table 1-410 R596 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0DPLL3_PHS1_TIMER_9:8R/W0x0 See Register 597

1.409 R597 (Offset = 0x255)

Return to the Summary Table.

Table 1-411 R597 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_PHS1_TIMERR/W0x0 Holdover exit phase slew control. Timer controlling update period.
ROM=Y, EEPROM=N

1.410 R602 (Offset = 0x25A)

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Table 1-412 R602 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0DPLL3_HIST_GAINR/W0x0 History filter gain
ROM=Y, EEPROM=N

1.411 R603 (Offset = 0x25B)

Return to the Summary Table.

Table 1-413 R603 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_PL_THRESHR/W0x0 Phase lock in-lock threshold
ROM=Y, EEPROM=N

1.412 R604 (Offset = 0x25C)

Return to the Summary Table.

Table 1-414 R604 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_PL_UNLK_THRESHR/W0x0 Phase lock out-of-lock threshold
ROM=Y, EEPROM=N

1.413 R605 (Offset = 0x25D)

Return to the Summary Table.

Table 1-415 R605 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_PHS1_THRESHR/W0x0 Holdover exit phase slew control. Change per timer event.
ROM=Y, EEPROM=N

1.414 R610 (Offset = 0x262)

Return to the Summary Table.

Table 1-416 R610 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5DPLL3_STATUS_PLR0x0 Readback the phase lock status
ROM=N, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.415 R611 (Offset = 0x263)

Return to the Summary Table.

Table 1-417 R611 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4DPLL3_DCO_SLEW_ACTIVER0x0 Readback DCO slew status
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.416 R614 (Offset = 0x266)

Return to the Summary Table.

Table 1-418 R614 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL3_FB_DIV_32:32R/W0x0 See Register 618

1.417 R615 (Offset = 0x267)

Return to the Summary Table.

Table 1-419 R615 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DIV_31:24R/W0x0 See Register 618

1.418 R616 (Offset = 0x268)

Return to the Summary Table.

Table 1-420 R616 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DIV_23:16R/W0x0 See Register 618

1.419 R617 (Offset = 0x269)

Return to the Summary Table.

Table 1-421 R617 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DIV_15:8R/W0x0 See Register 618

1.420 R618 (Offset = 0x26A)

Return to the Summary Table.

Table 1-422 R618 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DIVR/W0x0 DPLL Feedback Divider N Value used with DPLL3 feedback configuration 1. Divide value is programmed value except when using ZDM mode with FB div, actual divide value is +1.
ROM=Y, EEPROM=N

1.421 R619 (Offset = 0x26B)

Return to the Summary Table.

Table 1-423 R619 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_39:32R/W0x0 See Register 623

1.422 R620 (Offset = 0x26C)

Return to the Summary Table.

Table 1-424 R620 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_31:24R/W0x0 See Register 623

1.423 R621 (Offset = 0x26D)

Return to the Summary Table.

Table 1-425 R621 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_23:16R/W0x0 See Register 623

1.424 R622 (Offset = 0x26E)

Return to the Summary Table.

Table 1-426 R622 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_15:8R/W0x0 See Register 623

1.425 R623 (Offset = 0x26F)

Return to the Summary Table.

Table 1-427 R623 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUMR/W0x0 DPLL Feedback Divider Numerator Value used with DPLL3 feedback configuration 1
ROM=Y, EEPROM=N

1.426 R624 (Offset = 0x270)

Return to the Summary Table.

Table 1-428 R624 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DEN_39:32R/W0x0 See Register 628

1.427 R625 (Offset = 0x271)

Return to the Summary Table.

Table 1-429 R625 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DEN_31:24R/W0x0 See Register 628

1.428 R626 (Offset = 0x272)

Return to the Summary Table.

Table 1-430 R626 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DEN_23:16R/W0x0 See Register 628

1.429 R627 (Offset = 0x273)

Return to the Summary Table.

Table 1-431 R627 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DEN_15:8R/W0x0 See Register 628

1.430 R628 (Offset = 0x274)

Return to the Summary Table.

Table 1-432 R628 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_DENR/W0x0 DPLL Feedback Divider Denominator Value used with DPLL3 feedback configuration 1
ROM=Y, EEPROM=N

1.431 R629 (Offset = 0x275)

Return to the Summary Table.

Table 1-433 R629 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL3_FB2_DIV_32:32R/W0x0 See Register 633

1.432 R630 (Offset = 0x276)

Return to the Summary Table.

Table 1-434 R630 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DIV_31:24R/W0x0 See Register 633

1.433 R631 (Offset = 0x277)

Return to the Summary Table.

Table 1-435 R631 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DIV_23:16R/W0x0 See Register 633

1.434 R632 (Offset = 0x278)

Return to the Summary Table.

Table 1-436 R632 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DIV_15:8R/W0x0 See Register 633

1.435 R633 (Offset = 0x279)

Return to the Summary Table.

Table 1-437 R633 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DIVR/W0x0 DPLL Feedback Divider N Value used with DPLL3 feedback configuration 2. Divide value is programmed value except when using ZDM mode with FB div, actual divide value is +1.
ROM=Y, EEPROM=N

1.436 R634 (Offset = 0x27A)

Return to the Summary Table.

Table 1-438 R634 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_NUM_39:32R/W0x0 See Register 638

1.437 R635 (Offset = 0x27B)

Return to the Summary Table.

Table 1-439 R635 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_NUM_31:24R/W0x0 See Register 638

1.438 R636 (Offset = 0x27C)

Return to the Summary Table.

Table 1-440 R636 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_NUM_23:16R/W0x0 See Register 638

1.439 R637 (Offset = 0x27D)

Return to the Summary Table.

Table 1-441 R637 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_NUM_15:8R/W0x0 See Register 638

1.440 R638 (Offset = 0x27E)

Return to the Summary Table.

Table 1-442 R638 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_NUMR/W0x0 DPLL Feedback Divider Numerator Value used with DPLL3 feedback configuration 2
ROM=Y, EEPROM=N

1.441 R639 (Offset = 0x27F)

Return to the Summary Table.

Table 1-443 R639 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DEN_39:32R/W0x0 See Register 643

1.442 R640 (Offset = 0x280)

Return to the Summary Table.

Table 1-444 R640 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DEN_31:24R/W0x0 See Register 643

1.443 R641 (Offset = 0x281)

Return to the Summary Table.

Table 1-445 R641 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DEN_23:16R/W0x0 See Register 643

1.444 R642 (Offset = 0x282)

Return to the Summary Table.

Table 1-446 R642 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DEN_15:8R/W0x0 See Register 643

1.445 R643 (Offset = 0x283)

Return to the Summary Table.

Table 1-447 R643 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB2_DENR/W0x0 DPLL Feedback Divider Denominator Value used with DPLL3 feedback configuration 2
ROM=Y, EEPROM=N

1.446 R644 (Offset = 0x284)

Return to the Summary Table.

Table 1-448 R644 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5DPLL3_REF5_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF5. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
4DPLL3_REF4_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF4. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
3DPLL3_REF3_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF3. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
2DPLL3_REF2_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF2. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
1DPLL3_REF1_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF1. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2
0DPLL3_REF0_FB_SELR/W0x0 DPLL Feedback N, NUM, DEN select for REF0. When this bit is a 0, Value 1 is chosen for each of the three parameters. When it is set to a 1, Value 2 is used.
ROM=Y, EEPROM=N
  • 0x0 = FB Config 1
  • 0x1 = FB Config 2

1.447 R645 (Offset = 0x285)

Return to the Summary Table.

Table 1-449 R645 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:3RESERVEDR0x0 Reserved
2:0DPLL3_FB_MASH_ORDERR/W0x0 DPLL Feedback Divider MASH Order.
ROM=Y, EEPROM=N
  • 0x0 = Integer
  • 0x1 = 1st order
  • 0x2 = 2nd order
  • 0x3 = 3rd order
  • 0x4 = 4th order

1.448 R646 (Offset = 0x286)

Return to the Summary Table.

Table 1-450 R646 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0DPLL3_FB_FDEV_37:32R/W0x0 See Register 650

1.449 R647 (Offset = 0x287)

Return to the Summary Table.

Table 1-451 R647 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_FDEV_31:24R/W0x0 See Register 650

1.450 R648 (Offset = 0x288)

Return to the Summary Table.

Table 1-452 R648 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_FDEV_23:16R/W0x0 See Register 650

1.451 R649 (Offset = 0x289)

Return to the Summary Table.

Table 1-453 R649 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_FDEV_15:8R/W0x0 See Register 650

1.452 R650 (Offset = 0x28A)

Return to the Summary Table.

Table 1-454 R650 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_FDEVR/W0x0 DPLL Feedback Divider DCO Frequency Deviation Value
ROM=Y, EEPROM=N

1.453 R651 (Offset = 0x28B)

Return to the Summary Table.

Table 1-455 R651 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL3_FB_FDEV_UPDATER/W0x0 Increment/Decrement DPLL Feedback Numerator value with DPLL_FB_FDEV value
ROM=Y, EEPROM=N

1.454 R652 (Offset = 0x28C)

Return to the Summary Table.

Table 1-456 R652 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0DPLL3_FB_FDEV_ENR/W0x0 Enable DPLL DCO mode
ROM=Y, EEPROM=N

1.455 R653 (Offset = 0x28D)

Return to the Summary Table.

Table 1-457 R653 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_STAT_39:32R0x0 See Register 657

1.456 R654 (Offset = 0x28E)

Return to the Summary Table.

Table 1-458 R654 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_STAT_31:24R0x0 See Register 657

1.457 R655 (Offset = 0x28F)

Return to the Summary Table.

Table 1-459 R655 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_STAT_23:16R0x0 See Register 657

1.458 R656 (Offset = 0x290)

Return to the Summary Table.

Table 1-460 R656 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_STAT_15:8R0x0 See Register 657

1.459 R657 (Offset = 0x291)

Return to the Summary Table.

Table 1-461 R657 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_FB_NUM_STATR0x0 Readback DPLL Feedback Divider Numerator value as a result of DCO mode
ROM=N, EEPROM=N

1.460 R658 (Offset = 0x292)

Return to the Summary Table.

Table 1-462 R658 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3DPLL3_REF0_DBLR_ENR/W0x0 DPLL Reference 0 Doubler Enable
ROM=Y, EEPROM=N
2DPLL3_REF1_DBLR_ENR/W0x0 DPLL Reference 1 Doubler Enable
ROM=Y, EEPROM=N
1DPLL3_REF2_DBLR_ENR/W0x0 DPLL Reference 2 Doubler Enable
ROM=Y, EEPROM=N
0DPLL3_REF3_DBLR_ENR/W0x0 DPLL Reference 3 Doubler Enable
ROM=Y, EEPROM=N

1.461 R659 (Offset = 0x293)

Return to the Summary Table.

Table 1-463 R659 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF0_RDIV_15:8R/W0x0 See Register 660

1.462 R660 (Offset = 0x294)

Return to the Summary Table.

Table 1-464 R660 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF0_RDIVR/W0x0 DPLL Reference 0 R divider value
ROM=Y, EEPROM=N

1.463 R661 (Offset = 0x295)

Return to the Summary Table.

Table 1-465 R661 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF1_RDIV_15:8R/W0x0 See Register 662

1.464 R662 (Offset = 0x296)

Return to the Summary Table.

Table 1-466 R662 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF1_RDIVR/W0x0 DPLL Reference 1 R divider value
ROM=Y, EEPROM=N

1.465 R663 (Offset = 0x297)

Return to the Summary Table.

Table 1-467 R663 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF2_RDIV_15:8R/W0x0 See Register 664

1.466 R664 (Offset = 0x298)

Return to the Summary Table.

Table 1-468 R664 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF2_RDIVR/W0x0 DPLL Reference 2 R divider value
ROM=Y, EEPROM=N

1.467 R665 (Offset = 0x299)

Return to the Summary Table.

Table 1-469 R665 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF3_RDIV_15:8R/W0x0 See Register 666

1.468 R666 (Offset = 0x29A)

Return to the Summary Table.

Table 1-470 R666 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF3_RDIVR/W0x0 DPLL Reference 3 R divider value
ROM=Y, EEPROM=N

1.469 R667 (Offset = 0x29B)

Return to the Summary Table.

Table 1-471 R667 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF4_RDIV_15:8R/W0x0 See Register 668

1.470 R668 (Offset = 0x29C)

Return to the Summary Table.

Table 1-472 R668 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF4_RDIVR/W0x0 DPLL Reference 4 R divider value
ROM=Y, EEPROM=N

1.471 R669 (Offset = 0x29D)

Return to the Summary Table.

Table 1-473 R669 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF5_RDIV_15:8R/W0x0 See Register 670

1.472 R670 (Offset = 0x29E)

Return to the Summary Table.

Table 1-474 R670 Field Descriptions
BitFieldTypeResetDescription
7:0DPLL3_REF5_RDIVR/W0x0 DPLL Reference 5 R divider value
ROM=Y, EEPROM=N

1.473 R707 (Offset = 0x2C3)

Return to the Summary Table.

Table 1-475 R707 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_CP_PU_RR/W0x0 PLL charge pump pull-up resistor selection
ROM=Y, EEPROM=N
  • 0x0 = Disabled
  • 0x1 = 78 kΩ
  • 0x2 = 39 kΩ
  • 0x3 = 26 kΩ
  • 0x4 = 20 kΩ
  • 0x5 = 15.9 kΩ
  • 0x6 = 13.2 kΩ
  • 0x7 = 11.3 kΩ
  • 0x8 = 9.8 kΩ
  • 0x9 = 8.71 kΩ
  • 0xA = 7.83 kΩ
  • 0xB = 7.12 kΩ
  • 0xC = 6.58 kΩ
  • 0xD = 6.07 kΩ
  • 0xE = 5.63 kΩ
  • 0xF = 5.25 kΩ
  • 0x10 = 4.9 kΩ
  • 0x11 = 4.61 kΩ
  • 0x12 = 4.35 kΩ
  • 0x13 = 4.12 kΩ
  • 0x14 = 3.94 kΩ
  • 0x15 = 3.75 kΩ
  • 0x16 = 3.57 kΩ
  • 0x17 = 3.42 kΩ
  • 0x18 = 3.27 kΩ
  • 0x19 = 3.14 kΩ
  • 0x1A = 3.01 kΩ
  • 0x1B = 2.9 kΩ
  • 0x1C = 2.81 kΩ
  • 0x1D = 2.71 kΩ
  • 0x1E = 2.62 kΩ
  • 0x1F = 2.53 kΩ
  • 0x20 = 2.4 kΩ
  • 0x21 = 2.33 kΩ
  • 0x22 = 2.26 kΩ
  • 0x23 = 2.2 kΩ
  • 0x24 = 2.14 kΩ
  • 0x25 = 2.09 kΩ
  • 0x26 = 2.03 kΩ
  • 0x27 = 1.98 kΩ
  • 0x28 = 1.93 kΩ
  • 0x29 = 1.88 kΩ
  • 0x2A = 1.84 kΩ
  • 0x2B = 1.79 kΩ
  • 0x2C = 1.76 kΩ
  • 0x2D = 1.72 kΩ
  • 0x2E = 1.68 kΩ
  • 0x2F = 1.65 kΩ
  • 0x30 = 1.61 kΩ
  • 0x31 = 1.58 kΩ
  • 0x32 = 1.55 kΩ
  • 0x33 = 1.52 kΩ
  • 0x34 = 1.49 kΩ
  • 0x35 = 1.46 kΩ
  • 0x36 = 1.44 kΩ
  • 0x37 = 1.41 kΩ
  • 0x38 = 1.38 kΩ
  • 0x39 = 1.36 kΩ
  • 0x3A = 1.34 kΩ
  • 0x3B = 1.31 kΩ
  • 0x3C = 1.29 kΩ
  • 0x3D = 1.27 kΩ
  • 0x3E = 1.25 kΩ
  • 0x3F = 1.23 kΩ
  • 0x40 = 1.2 kΩ
  • 0x41 = 1.18 kΩ
  • 0x42 = 1.16 kΩ
  • 0x43 = 1.15 kΩ
  • 0x44 = 1.13 kΩ
  • 0x45 = 1.12 kΩ
  • 0x46 = 1.1 kΩ
  • 0x47 = 1.08 kΩ
  • 0x48 = 1.07 kΩ
  • 0x49 = 1.05 kΩ
  • 0x4A = 1.04 kΩ
  • 0x4B = 1.03 kΩ
  • 0x4C = 1.01 kΩ
  • 0x4D = 1 kΩ
  • 0x4E = 0.989 kΩ
  • 0x4F = 0.977 kΩ
  • 0x50 = 0.964 kΩ
  • 0x51 = 0.952 kΩ
  • 0x52 = 0.941 kΩ
  • 0x53 = 0.929 kΩ
  • 0x54 = 0.92 kΩ
  • 0x55 = 0.909 kΩ
  • 0x56 = 0.898 kΩ
  • 0x57 = 0.888 kΩ
  • 0x58 = 0.878 kΩ
  • 0x59 = 0.868 kΩ
  • 0x5A = 0.858 kΩ
  • 0x5B = 0.849 kΩ
  • 0x5C = 0.841 kΩ
  • 0x5D = 0.832 kΩ
  • 0x5E = 0.823 kΩ
  • 0x5F = 0.814 kΩ
  • 0x60 = 0.8 kΩ
  • 0x61 = 0.792 kΩ
  • 0x62 = 0.784 kΩ
  • 0x63 = 0.776 kΩ
  • 0x64 = 0.769 kΩ
  • 0x65 = 0.762 kΩ
  • 0x66 = 0.754 kΩ
  • 0x67 = 0.747 kΩ
  • 0x68 = 0.74 kΩ
  • 0x69 = 0.733 kΩ
  • 0x6A = 0.726 kΩ
  • 0x6B = 0.719 kΩ
  • 0x6C = 0.713 kΩ
  • 0x6D = 0.707 kΩ
  • 0x6E = 0.7 kΩ
  • 0x6F = 0.694 kΩ
  • 0x70 = 0.688 kΩ
  • 0x71 = 0.682 kΩ
  • 0x72 = 0.676 kΩ
  • 0x73 = 0.67 kΩ
  • 0x74 = 0.665 kΩ
  • 0x75 = 0.659 kΩ
  • 0x76 = 0.654 kΩ
  • 0x77 = 0.648 kΩ
  • 0x78 = 0.643 kΩ
  • 0x79 = 0.637 kΩ
  • 0x7A = 0.632 kΩ
  • 0x7B = 0.627 kΩ
  • 0x7C = 0.623 kΩ
  • 0x7D = 0.618 kΩ
  • 0x7E = 0.613 kΩ
  • 0x7F = 0.608 kΩ
  • 0x80 = 0.6 kΩ
  • 0x81 = 0.595 kΩ
  • 0x82 = 0.591 kΩ
  • 0x83 = 0.586 kΩ
  • 0x84 = 0.583 kΩ
  • 0x85 = 0.578 kΩ
  • 0x86 = 0.574 kΩ
  • 0x87 = 0.57 kΩ
  • 0x88 = 0.565 kΩ
  • 0x89 = 0.561 kΩ
  • 0x8A = 0.557 kΩ
  • 0x8B = 0.553 kΩ
  • 0x8C = 0.55 kΩ
  • 0x8D = 0.546 kΩ
  • 0x8E = 0.542 kΩ
  • 0x8F = 0.538 kΩ
  • 0x90 = 0.535 kΩ
  • 0x91 = 0.531 kΩ
  • 0x92 = 0.527 kΩ
  • 0x93 = 0.524 kΩ
  • 0x94 = 0.521 kΩ
  • 0x95 = 0.517 kΩ
  • 0x96 = 0.514 kΩ
  • 0x97 = 0.51 kΩ
  • 0x98 = 0.507 kΩ
  • 0x99 = 0.504 kΩ
  • 0x9A = 0.5 kΩ
  • 0x9B = 0.497 kΩ
  • 0x9C = 0.494 kΩ
  • 0x9D = 0.491 kΩ
  • 0x9E = 0.488 kΩ
  • 0x9F = 0.485 kΩ
  • 0xA0 = 0.48 kΩ
  • 0xA1 = 0.477 kΩ
  • 0xA2 = 0.474 kΩ
  • 0xA3 = 0.471 kΩ
  • 0xA4 = 0.469 kΩ
  • 0xA5 = 0.466 kΩ
  • 0xA6 = 0.463 kΩ
  • 0xA7 = 0.46 kΩ
  • 0xA8 = 0.458 kΩ
  • 0xA9 = 0.455 kΩ
  • 0xAA = 0.452 kΩ
  • 0xAB = 0.45 kΩ
  • 0xAC = 0.447 kΩ
  • 0xAD = 0.445 kΩ
  • 0xAE = 0.442 kΩ
  • 0xAF = 0.44 kΩ
  • 0xB0 = 0.437 kΩ
  • 0xB1 = 0.435 kΩ
  • 0xB2 = 0.432 kΩ
  • 0xB3 = 0.43 kΩ
  • 0xB4 = 0.428 kΩ
  • 0xB5 = 0.425 kΩ
  • 0xB6 = 0.423 kΩ
  • 0xB7 = 0.421 kΩ
  • 0xB8 = 0.419 kΩ
  • 0xB9 = 0.416 kΩ
  • 0xBA = 0.414 kΩ
  • 0xBB = 0.412 kΩ
  • 0xBC = 0.41 kΩ
  • 0xBD = 0.408 kΩ
  • 0xBE = 0.406 kΩ
  • 0xBF = 0.404 kΩ
  • 0xC0 = 0.4 kΩ
  • 0xC1 = 0.398 kΩ
  • 0xC2 = 0.396 kΩ
  • 0xC3 = 0.394 kΩ
  • 0xC4 = 0.392 kΩ
  • 0xC5 = 0.39 kΩ
  • 0xC6 = 0.388 kΩ
  • 0xC7 = 0.386 kΩ
  • 0xC8 = 0.384 kΩ
  • 0xC9 = 0.382 kΩ
  • 0xCA = 0.381 kΩ
  • 0xCB = 0.379 kΩ
  • 0xCC = 0.377 kΩ
  • 0xCD = 0.375 kΩ
  • 0xCE = 0.373 kΩ
  • 0xCF = 0.372 kΩ
  • 0xD0 = 0.37 kΩ
  • 0xD1 = 0.368 kΩ
  • 0xD2 = 0.366 kΩ
  • 0xD3 = 0.365 kΩ
  • 0xD4 = 0.363 kΩ
  • 0xD5 = 0.361 kΩ
  • 0xD6 = 0.36 kΩ
  • 0xD7 = 0.358 kΩ
  • 0xD8 = 0.356 kΩ
  • 0xD9 = 0.355 kΩ
  • 0xDA = 0.353 kΩ
  • 0xDB = 0.352 kΩ
  • 0xDC = 0.35 kΩ
  • 0xDD = 0.349 kΩ
  • 0xDE = 0.347 kΩ
  • 0xDF = 0.345 kΩ
  • 0xE0 = 0.343 kΩ
  • 0xE1 = 0.341 kΩ
  • 0xE2 = 0.34 kΩ
  • 0xE3 = 0.338 kΩ
  • 0xE4 = 0.337 kΩ
  • 0xE5 = 0.336 kΩ
  • 0xE6 = 0.334 kΩ
  • 0xE7 = 0.333 kΩ
  • 0xE8 = 0.331 kΩ
  • 0xE9 = 0.33 kΩ
  • 0xEA = 0.328 kΩ
  • 0xEB = 0.327 kΩ
  • 0xEC = 0.326 kΩ
  • 0xED = 0.325 kΩ
  • 0xEE = 0.323 kΩ
  • 0xEF = 0.322 kΩ
  • 0xF0 = 0.32 kΩ
  • 0xF1 = 0.319 kΩ
  • 0xF2 = 0.318 kΩ
  • 0xF3 = 0.317 kΩ
  • 0xF4 = 0.315 kΩ
  • 0xF5 = 0.314 kΩ
  • 0xF6 = 0.313 kΩ
  • 0xF7 = 0.312 kΩ
  • 0xF8 = 0.31 kΩ
  • 0xF9 = 0.309 kΩ
  • 0xFA = 0.308 kΩ
  • 0xFB = 0.307 kΩ
  • 0xFC = 0.306 kΩ
  • 0xFD = 0.304 kΩ
  • 0xFE = 0.303 kΩ
  • 0xFF = 0.302 kΩ

1.474 R708 (Offset = 0x2C4)

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Table 1-476 R708 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1:0PLL1_CPGR/W0x3 PLL charge pump gain Pump up/down.
ROM=Y, EEPROM=Y
  • 0x0 = 1.6 mA
  • 0x1 = 3.2 mA
  • 0x2 = 4.8 mA
  • 0x3 = 6.4 mA

1.475 R709 (Offset = 0x2C5)

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Table 1-477 R709 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL1_LF_R2R/W0x0 PLL Loop Filter R2 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.262 kΩ
  • 0x2 = 0.357 kΩ
  • 0x3 = 0.166 kΩ
  • 0x4 = 0.642 kΩ
  • 0x5 = 0.199 kΩ
  • 0x6 = 0.244 kΩ
  • 0x7 = 0.142 kΩ
  • 0x8 = 1.14 kΩ
  • 0x9 = 0.222 kΩ
  • 0xA = 0.283 kΩ
  • 0xB = 0.152 kΩ
  • 0xC = 0.425 kΩ
  • 0xD = 0.177 kΩ
  • 0xE = 0.21 kΩ
  • 0xF = 0.132 kΩ
  • 0x10 = 0.847 kΩ
  • 0x11 = 1.06 kΩ
  • 0x12 = 1.16 kΩ
  • 0x13 = 0.966 kΩ
  • 0x14 = 1.44 kΩ
  • 0x15 = 0.998 kΩ
  • 0x16 = 1.04 kΩ
  • 0x17 = 0.941 kΩ
  • 0x18 = 1.94 kΩ
  • 0x19 = 1.02 kΩ
  • 0x1A = 1.08 kΩ
  • 0x1B = 0.951 kΩ
  • 0x1C = 1.22 kΩ
  • 0x1D = 0.976 kΩ
  • 0x1E = 1.01 kΩ
  • 0x1F = 0.931 kΩ
  • 0x20 = 1.66 kΩ
  • 0x21 = 1.88 kΩ
  • 0x22 = 1.97 kΩ
  • 0x23 = 1.78 kΩ
  • 0x24 = 2.26 kΩ
  • 0x25 = 1.81 kΩ
  • 0x26 = 1.86 kΩ
  • 0x27 = 1.76 kΩ
  • 0x28 = 2.75 kΩ
  • 0x29 = 1.84 kΩ
  • 0x2A = 1.9 kΩ
  • 0x2B = 1.77 kΩ
  • 0x2C = 2.04 kΩ
  • 0x2D = 1.79 kΩ
  • 0x2E = 1.82 kΩ
  • 0x2F = 1.75 kΩ
  • 0x30 = 2.46 kΩ
  • 0x31 = 2.68 kΩ
  • 0x32 = 2.77 kΩ
  • 0x33 = 2.58 kΩ
  • 0x34 = 3.06 kΩ
  • 0x35 = 2.61 kΩ
  • 0x36 = 2.66 kΩ
  • 0x37 = 2.56 kΩ
  • 0x38 = 3.55 kΩ
  • 0x39 = 2.64 kΩ
  • 0x3A = 2.7 kΩ
  • 0x3B = 2.57 kΩ
  • 0x3C = 2.84 kΩ
  • 0x3D = 2.59 kΩ
  • 0x3E = 2.62 kΩ
  • 0x3F = 2.55 kΩ

1.476 R710 (Offset = 0x2C6)

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Table 1-478 R710 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL1_LF_R3R/W0x0 PLL Loop Filter R3 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.277 kΩ
  • 0x2 = 0.657 kΩ
  • 0x3 = 0.214 kΩ
  • 0x4 = 0.754 kΩ
  • 0x5 = 0.221 kΩ
  • 0x6 = 0.375 kΩ
  • 0x7 = 0.183 kΩ
  • 0x8 = 0.863 kΩ
  • 0x9 = 1.08 kΩ
  • 0xA = 1.46 kΩ
  • 0xB = 1.01 kΩ
  • 0xC = 1.55 kΩ
  • 0xD = 1.02 kΩ
  • 0xE = 1.17 kΩ
  • 0xF = 0.982 kΩ
  • 0x10 = 1.68 kΩ
  • 0x11 = 1.89 kΩ
  • 0x12 = 2.27 kΩ
  • 0x13 = 1.83 kΩ
  • 0x14 = 2.37 kΩ
  • 0x15 = 1.84 kΩ
  • 0x16 = 1.99 kΩ
  • 0x17 = 1.8 kΩ
  • 0x18 = 2.48 kΩ
  • 0x19 = 2.69 kΩ
  • 0x1A = 3.07 kΩ
  • 0x1B = 2.63 kΩ
  • 0x1C = 3.17 kΩ
  • 0x1D = 2.63 kΩ
  • 0x1E = 2.79 kΩ
  • 0x1F = 2.6 kΩ
  • 0x20 = 3.31 kΩ
  • 0x21 = 3.52 kΩ
  • 0x22 = 3.9 kΩ
  • 0x23 = 3.46 kΩ
  • 0x24 = 4 kΩ
  • 0x25 = 3.47 kΩ
  • 0x26 = 3.62 kΩ
  • 0x27 = 3.43 kΩ
  • 0x28 = 4.11 kΩ
  • 0x29 = 4.32 kΩ
  • 0x2A = 4.7 kΩ
  • 0x2B = 4.26 kΩ
  • 0x2C = 4.8 kΩ
  • 0x2D = 4.26 kΩ
  • 0x2E = 4.42 kΩ
  • 0x2F = 4.23 kΩ
  • 0x30 = 4.92 kΩ
  • 0x31 = 5.14 kΩ
  • 0x32 = 5.52 kΩ
  • 0x33 = 5.07 kΩ
  • 0x34 = 5.61 kΩ
  • 0x35 = 5.08 kΩ
  • 0x36 = 5.23 kΩ
  • 0x37 = 5.04 kΩ
  • 0x38 = 5.72 kΩ
  • 0x39 = 5.94 kΩ
  • 0x3A = 6.32 kΩ
  • 0x3B = 5.87 kΩ
  • 0x3C = 6.41 kΩ
  • 0x3D = 5.88 kΩ
  • 0x3E = 6.03 kΩ
  • 0x3F = 5.84 kΩ

1.477 R711 (Offset = 0x2C7)

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Table 1-479 R711 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL1_LF_R4R/W0x0 PLL Loop Filter R4 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.277 kΩ
  • 0x2 = 0.657 kΩ
  • 0x3 = 0.214 kΩ
  • 0x4 = 0.754 kΩ
  • 0x5 = 0.221 kΩ
  • 0x6 = 0.375 kΩ
  • 0x7 = 0.183 kΩ
  • 0x8 = 0.863 kΩ
  • 0x9 = 1.08 kΩ
  • 0xA = 1.46 kΩ
  • 0xB = 1.01 kΩ
  • 0xC = 1.55 kΩ
  • 0xD = 1.02 kΩ
  • 0xE = 1.17 kΩ
  • 0xF = 0.982 kΩ
  • 0x10 = 1.68 kΩ
  • 0x11 = 1.89 kΩ
  • 0x12 = 2.27 kΩ
  • 0x13 = 1.83 kΩ
  • 0x14 = 2.37 kΩ
  • 0x15 = 1.84 kΩ
  • 0x16 = 1.99 kΩ
  • 0x17 = 1.8 kΩ
  • 0x18 = 2.48 kΩ
  • 0x19 = 2.69 kΩ
  • 0x1A = 3.07 kΩ
  • 0x1B = 2.63 kΩ
  • 0x1C = 3.17 kΩ
  • 0x1D = 2.63 kΩ
  • 0x1E = 2.79 kΩ
  • 0x1F = 2.6 kΩ
  • 0x20 = 3.31 kΩ
  • 0x21 = 3.52 kΩ
  • 0x22 = 3.9 kΩ
  • 0x23 = 3.46 kΩ
  • 0x24 = 4 kΩ
  • 0x25 = 3.47 kΩ
  • 0x26 = 3.62 kΩ
  • 0x27 = 3.43 kΩ
  • 0x28 = 4.11 kΩ
  • 0x29 = 4.32 kΩ
  • 0x2A = 4.7 kΩ
  • 0x2B = 4.26 kΩ
  • 0x2C = 4.8 kΩ
  • 0x2D = 4.26 kΩ
  • 0x2E = 4.42 kΩ
  • 0x2F = 4.23 kΩ
  • 0x30 = 4.92 kΩ
  • 0x31 = 5.14 kΩ
  • 0x32 = 5.52 kΩ
  • 0x33 = 5.07 kΩ
  • 0x34 = 5.61 kΩ
  • 0x35 = 5.08 kΩ
  • 0x36 = 5.23 kΩ
  • 0x37 = 5.04 kΩ
  • 0x38 = 5.72 kΩ
  • 0x39 = 5.94 kΩ
  • 0x3A = 6.32 kΩ
  • 0x3B = 5.87 kΩ
  • 0x3C = 6.41 kΩ
  • 0x3D = 5.88 kΩ
  • 0x3E = 6.03 kΩ
  • 0x3F = 5.84 kΩ

1.478 R712 (Offset = 0x2C8)

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Table 1-480 R712 Field Descriptions
BitFieldTypeResetDescription
7:6PLL1_DISABLE_3RD4THR/W0x0 PLL Loop Filter Disconnects C3 and C4
ROM=Y, EEPROM=N
  • 0x0 = C3/C4 Disconnected
  • 0x1 = C3=Enabled, C4=Disconnected
  • 0x2 = C3=Disconnected, C4=Enabled
  • 0x3 = C3=Enabled, C4=Enabled
5:3PLL1_LF_C3R/W0x0 PLL Loop Filter C3 setting
ROM=Y, EEPROM=N
  • 0x0 = 0 pF
  • 0x1 = 10 pF
  • 0x2 = 20 pF
  • 0x3 = 30 pF
  • 0x4 = 40 pF
  • 0x5 = 50 pF
  • 0x6 = 60 pF
  • 0x7 = 70 pF
2:0PLL1_LF_C4R/W0x0 PLL Loop Filter C4 setting
ROM=Y, EEPROM=N
  • 0x0 = 0 pF
  • 0x1 = 10 pF
  • 0x2 = 20 pF
  • 0x3 = 30 pF
  • 0x4 = 40 pF
  • 0x5 = 50 pF
  • 0x6 = 60 pF
  • 0x7 = 70 pF

1.479 R713 (Offset = 0x2C9)

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Table 1-481 R713 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL1_RDIV_8:8R/W0x0 See Register 714

1.480 R714 (Offset = 0x2CA)

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Table 1-482 R714 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_RDIVR/W0x1 PLL R Divider
ROM=Y, EEPROM=Y

1.481 R715 (Offset = 0x2CB)

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Table 1-483 R715 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4PLL1_RDIV_XO_ENR/W0x0 APLL reference source is from XO. Must also enable XO to drive this APLL with XO_OUT_BUF_EN[1] = 1
ROM=Y, EEPROM=Y
3PLL1_RDIV_XO_DBLR_ENR/W0x0 Enables XO Doubler
ROM=Y, EEPROM=Y
2PLL1_RDIV_BYPASS_ENR/W0x0 Bypass R Divider
ROM=Y, EEPROM=Y
1:0PLL1_RDIV_MUX_SELR/W0x0 Select R Divider input. When enabling reference from feedback divider, the APLL PLLx_VCO_BUF_2REF_EN bit must also be set appropriately.
ROM=Y, EEPROM=Y
  • 0x0 = XO
  • 0x1 = VCO2 feedback divider
  • 0x2 = VCO3 feedback divider

1.482 R716 (Offset = 0x2CC)

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Table 1-484 R716 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL1_NDIV_8:8R/W0x0 See Register 717

1.483 R717 (Offset = 0x2CD)

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Table 1-485 R717 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NDIVR/W0x40 PLL N Divider
ROM=Y, EEPROM=Y

1.484 R718 (Offset = 0x2CE)

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Table 1-486 R718 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NUM_MSBR/W0x4C When PLL1_MODE is set for 24 bit fractional. PLL1_NUM_MSB is effective PLL1_NUM[23:16]. Other PLL1_NUM and PLL1_DEN bits in programmable mode are in PLL1_NUM field. When in 40-bit fixed denominator PLL mode, then PLL1_NUM_MSB is unused.
ROM=Y, EEPROM=Y

1.485 R719 (Offset = 0x2CF)

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Table 1-487 R719 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NUM_39:32R/W0x4C See Register 723

1.486 R720 (Offset = 0x2D0)

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Table 1-488 R720 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NUM_31:24R/W0xE7 See Register 723

1.487 R721 (Offset = 0x2D1)

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Table 1-489 R721 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NUM_23:16R/W0xC5 See Register 723

1.488 R722 (Offset = 0x2D2)

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Table 1-490 R722 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NUM_15:8R/W0x1 See Register 723

1.489 R723 (Offset = 0x2D3)

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Table 1-491 R723 Field Descriptions
BitFieldTypeResetDescription
7:0PLL1_NUMR/W0xE When PLL1_MODE = 1 (40-bit fixed denominator) mode then PLL1_NUM contains the APLL1 numerator. When PLL1_MODE = 0 (24-bit programmable denominator) then PLL1_NUM[23:0] stores the programmable PLL1 denominator and PLL1_NUM[39:24] stores the 16 LSBs of the PLL1 numerator. Total PLL1 numerator is calculated with PLL1_NUM_MSB as the 8 MSBs. In 24-bit programmable denominator mode PLL1_NUM[23:0] = 0 is 224.
ROM=Y, EEPROM=Y

1.490 R724 (Offset = 0x2D4)

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Table 1-492 R724 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:4PLL1_DTHRMODER/W0x0 PLL MASH Dither Mode
ROM=Y, EEPROM=N
  • 0x0 = Constant Dither MACC2
  • 0x1 = Constant Dither MACC2 and MACC3
  • 0x2 = LFSR Dither MACC2
  • 0x3 = Dither Disabled
3:1PLL1_ORDERR/W0x0 PLL MASH Order
ROM=Y, EEPROM=N
  • 0x0 = Integer Mode Divider
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
0PLL1_MODER/W0x1 In APLL 24-bit num/den mode, APLL denominator is programmable. Recommended not for use with DPLL mode. In 24-bit mode, the denominator is stored in PLL1_NUM[23:0] The numerator is stored in (PLL1_NUM_MSB << 16) + PLL1_NUM[39:24].

In APLL 40-bit mode, APLL denominator is fixed. For use with DPLL.
ROM=Y, EEPROM=Y
  • 0x0 = APLL 24-bit num/den
  • 0x1 = APLL 40-bit num (Req for DPLL)

1.491 R725 (Offset = 0x2D5)

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Table 1-493 R725 Field Descriptions
BitFieldTypeResetDescription
7:0APLL1_NUM_STAT_39:32R0x0 See Register 729

1.492 R726 (Offset = 0x2D6)

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Table 1-494 R726 Field Descriptions
BitFieldTypeResetDescription
7:0APLL1_NUM_STAT_31:24R0x0 See Register 729

1.493 R727 (Offset = 0x2D7)

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Table 1-495 R727 Field Descriptions
BitFieldTypeResetDescription
7:0APLL1_NUM_STAT_23:16R0x0 See Register 729

1.494 R728 (Offset = 0x2D8)

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Table 1-496 R728 Field Descriptions
BitFieldTypeResetDescription
7:0APLL1_NUM_STAT_15:8R0x0 See Register 729

1.495 R729 (Offset = 0x2D9)

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Table 1-497 R729 Field Descriptions
BitFieldTypeResetDescription
7:0APLL1_NUM_STATR0x0 Readback current effective APLL1 Numerator after FDEV and/or DPLL correction
ROM=N, EEPROM=N

1.496 R731 (Offset = 0x2DB)

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Table 1-498 R731 Field Descriptions
BitFieldTypeResetDescription
7PLL1_PRI_DIV_SYNC_ENR/W0x0 PLL1 P1 Divider Sync Enable. Enables synchronization of PLL1 P1 post-divider.
ROM=Y, EEPROM=N
6PLL1_PRI_DIV_ENR/W0x0 Enables the VCO1 P1 divider
ROM=Y, EEPROM=Y
5:3PLL1_PRI_DIVR/W0x2 Sets the VCO post-divider VCO1 P1 from 2 to 7.
ROM=Y, EEPROM=Y
  • 0x0 = 2 (Reserved)
  • 0x1 = 2
  • 0x2 = 3
  • 0x3 = 4
  • 0x4 = 5
  • 0x5 = 6
  • 0x6 = 7
2PLL1_P1_DIV_OUT0_1_ENR/W0x0 Enables VCO1 P1 divider output driver to channel output bank OUT0_1
ROM=Y, EEPROM=Y
1PLL1_P1_DIV_OUT2_3_ENR/W0x0 Enables VCO1 P1 divider output driver to channel output bank OUT2_3
ROM=Y, EEPROM=Y
0PLL1_P1_DIV_OUT14_15_ENR/W0x0 Enables VCO1 P1 divider output driver to channel output bank OUT14_15
ROM=Y, EEPROM=Y

1.497 R732 (Offset = 0x2DC)

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Table 1-499 R732 Field Descriptions
BitFieldTypeResetDescription
7PLL1_SEC_DIV_SYNC_ENR/W0x0 PLL1 P2 Divider Sync Enable. Enables synchronization of PLL1 P2 post-divider.
ROM=Y, EEPROM=N
6PLL1_SEC_DIV_ENR/W0x0 Enables the VCO1 P2 divider
ROM=Y, EEPROM=Y
5:3PLL1_SEC_DIVR/W0x2 Sets the VCO post-divider VCO1 P2 from 2 to 7.
ROM=Y, EEPROM=Y
  • 0x0 = 2 (Reserved)
  • 0x1 = 2
  • 0x2 = 3
  • 0x3 = 4
  • 0x4 = 5
  • 0x5 = 6
  • 0x6 = 7
2PLL1_P2_DIV_OUT0_1_ENR/W0x0 Enables the VCO1 P2 divider output driver to channel output bank OUT0_1
ROM=Y, EEPROM=Y
1RESERVEDR0x0 Enables the VCO1 P2 divider output driver to channel output bank Reserved
ROM=Y, EEPROM=Y
0RESERVEDR0x0 Enables the VCO1 P2 divider output driver to channel output bank Reserved
ROM=Y, EEPROM=Y

1.498 R733 (Offset = 0x2DD)

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Table 1-500 R733 Field Descriptions
BitFieldTypeResetDescription
7PLL1_VCO_BUF_ENR/W0x0 Enables the VCO1 Buffer which drives the DPLL feedback, reference window detector, DPLL reference for cascade mode, and test mode
ROM=Y, EEPROM=N
6:5PLL1_VCO_BUF_2REF_ENR/W0x0 Enables the APLL1 Div-by-4 cascade divider to APLL2/3 reference input for cascade mode. [0] - > APLL2, [1] -> APLL3
ROM=Y, EEPROM=Y
4PLL1_VCO_BUF_2DPLL_ENR/W0x0 Enables the VCO1 Buffer output driver to DPLL feedback divider
ROM=Y, EEPROM=N
3RESERVEDR0x0 Reserved
2PLL1_VCO_BUF_PPM_CHECK_ENR/W0x0 Enables the APLL1 Div-by-4/8 cascade divider to DPLL/PPM frequency detector
ROM=Y, EEPROM=N
1:0PLL1_VCO_BUF_FB_TDC_ENR/W0x0 Enables APLL1 Div-by-8 cacade divider to TDC2 and TDC3 for cascade mode [0] = TDC2 driver enable [1] = TDC3 driver enable
ROM=Y, EEPROM=N

1.499 R736 (Offset = 0x2E0)

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Table 1-501 R736 Field Descriptions
BitFieldTypeResetDescription
7PLL1_NCLK_TEST_ENR/W0x0 Unused
ROM=N, EEPROM=N
6:4RESERVEDR0x0 Reserved
3PLL1_RDIV_OUTPUT_ENR/W0x0 If GPIOx_SEL selects PLL1 R/2 as an output. Then this bit must be set along with STATUS_MUX_DIV2_EN=1.
ROM=N, EEPROM=N
2:0RESERVEDR0x0 Reserved

1.500 R741 (Offset = 0x2E5)

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Table 1-502 R741 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5PLL1_VM_INSIDER0x0 Denotes if the VCO tuning voltage is within operational range.
ROM=N, EEPROM=N
4PLL1_VM_HIR0x0 Denotes if the charge pump voltage is too high and outside range. If PLL1_VM_INSIDE = 0 and VM_HI = 0, then charge pump voltage is too low.
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.501 R745 (Offset = 0x2E9)

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Table 1-503 R745 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5PLL1_NDIV_OUTPUT_ENR/W0x0 If GPIOx_SEL selects PLL1 N/2 as an output. Then this bit must be set along with STATUS_MUX_DIV2_EN=1.
ROM=N, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.502 R746 (Offset = 0x2EA)

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Table 1-504 R746 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL1_VCO_PREBUF_ENR/W0x0 Set to same value as APLL1_EN.
ROM=Y, EEPROM=Y

1.503 R773 (Offset = 0x305)

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Table 1-505 R773 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0RESERVEDR0x0 Reserved

1.504 R777 (Offset = 0x309)

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Table 1-506 R777 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_CP_PU_RR/W0x0 PLL charge pump pull-up resistor selection
ROM=Y, EEPROM=N
  • 0x0 = Disabled
  • 0x1 = 78 kΩ
  • 0x2 = 39 kΩ
  • 0x3 = 26 kΩ
  • 0x4 = 20 kΩ
  • 0x5 = 15.9 kΩ
  • 0x6 = 13.2 kΩ
  • 0x7 = 11.3 kΩ
  • 0x8 = 9.8 kΩ
  • 0x9 = 8.71 kΩ
  • 0xA = 7.83 kΩ
  • 0xB = 7.12 kΩ
  • 0xC = 6.58 kΩ
  • 0xD = 6.07 kΩ
  • 0xE = 5.63 kΩ
  • 0xF = 5.25 kΩ
  • 0x10 = 4.9 kΩ
  • 0x11 = 4.61 kΩ
  • 0x12 = 4.35 kΩ
  • 0x13 = 4.12 kΩ
  • 0x14 = 3.94 kΩ
  • 0x15 = 3.75 kΩ
  • 0x16 = 3.57 kΩ
  • 0x17 = 3.42 kΩ
  • 0x18 = 3.27 kΩ
  • 0x19 = 3.14 kΩ
  • 0x1A = 3.01 kΩ
  • 0x1B = 2.9 kΩ
  • 0x1C = 2.81 kΩ
  • 0x1D = 2.71 kΩ
  • 0x1E = 2.62 kΩ
  • 0x1F = 2.53 kΩ
  • 0x20 = 2.4 kΩ
  • 0x21 = 2.33 kΩ
  • 0x22 = 2.26 kΩ
  • 0x23 = 2.2 kΩ
  • 0x24 = 2.14 kΩ
  • 0x25 = 2.09 kΩ
  • 0x26 = 2.03 kΩ
  • 0x27 = 1.98 kΩ
  • 0x28 = 1.93 kΩ
  • 0x29 = 1.88 kΩ
  • 0x2A = 1.84 kΩ
  • 0x2B = 1.79 kΩ
  • 0x2C = 1.76 kΩ
  • 0x2D = 1.72 kΩ
  • 0x2E = 1.68 kΩ
  • 0x2F = 1.65 kΩ
  • 0x30 = 1.61 kΩ
  • 0x31 = 1.58 kΩ
  • 0x32 = 1.55 kΩ
  • 0x33 = 1.52 kΩ
  • 0x34 = 1.49 kΩ
  • 0x35 = 1.46 kΩ
  • 0x36 = 1.44 kΩ
  • 0x37 = 1.41 kΩ
  • 0x38 = 1.38 kΩ
  • 0x39 = 1.36 kΩ
  • 0x3A = 1.34 kΩ
  • 0x3B = 1.31 kΩ
  • 0x3C = 1.29 kΩ
  • 0x3D = 1.27 kΩ
  • 0x3E = 1.25 kΩ
  • 0x3F = 1.23 kΩ
  • 0x40 = 1.2 kΩ
  • 0x41 = 1.18 kΩ
  • 0x42 = 1.16 kΩ
  • 0x43 = 1.15 kΩ
  • 0x44 = 1.13 kΩ
  • 0x45 = 1.12 kΩ
  • 0x46 = 1.1 kΩ
  • 0x47 = 1.08 kΩ
  • 0x48 = 1.07 kΩ
  • 0x49 = 1.05 kΩ
  • 0x4A = 1.04 kΩ
  • 0x4B = 1.03 kΩ
  • 0x4C = 1.01 kΩ
  • 0x4D = 1 kΩ
  • 0x4E = 0.989 kΩ
  • 0x4F = 0.977 kΩ
  • 0x50 = 0.964 kΩ
  • 0x51 = 0.952 kΩ
  • 0x52 = 0.941 kΩ
  • 0x53 = 0.929 kΩ
  • 0x54 = 0.92 kΩ
  • 0x55 = 0.909 kΩ
  • 0x56 = 0.898 kΩ
  • 0x57 = 0.888 kΩ
  • 0x58 = 0.878 kΩ
  • 0x59 = 0.868 kΩ
  • 0x5A = 0.858 kΩ
  • 0x5B = 0.849 kΩ
  • 0x5C = 0.841 kΩ
  • 0x5D = 0.832 kΩ
  • 0x5E = 0.823 kΩ
  • 0x5F = 0.814 kΩ
  • 0x60 = 0.8 kΩ
  • 0x61 = 0.792 kΩ
  • 0x62 = 0.784 kΩ
  • 0x63 = 0.776 kΩ
  • 0x64 = 0.769 kΩ
  • 0x65 = 0.762 kΩ
  • 0x66 = 0.754 kΩ
  • 0x67 = 0.747 kΩ
  • 0x68 = 0.74 kΩ
  • 0x69 = 0.733 kΩ
  • 0x6A = 0.726 kΩ
  • 0x6B = 0.719 kΩ
  • 0x6C = 0.713 kΩ
  • 0x6D = 0.707 kΩ
  • 0x6E = 0.7 kΩ
  • 0x6F = 0.694 kΩ
  • 0x70 = 0.688 kΩ
  • 0x71 = 0.682 kΩ
  • 0x72 = 0.676 kΩ
  • 0x73 = 0.67 kΩ
  • 0x74 = 0.665 kΩ
  • 0x75 = 0.659 kΩ
  • 0x76 = 0.654 kΩ
  • 0x77 = 0.648 kΩ
  • 0x78 = 0.643 kΩ
  • 0x79 = 0.637 kΩ
  • 0x7A = 0.632 kΩ
  • 0x7B = 0.627 kΩ
  • 0x7C = 0.623 kΩ
  • 0x7D = 0.618 kΩ
  • 0x7E = 0.613 kΩ
  • 0x7F = 0.608 kΩ
  • 0x80 = 0.6 kΩ
  • 0x81 = 0.595 kΩ
  • 0x82 = 0.591 kΩ
  • 0x83 = 0.586 kΩ
  • 0x84 = 0.583 kΩ
  • 0x85 = 0.578 kΩ
  • 0x86 = 0.574 kΩ
  • 0x87 = 0.57 kΩ
  • 0x88 = 0.565 kΩ
  • 0x89 = 0.561 kΩ
  • 0x8A = 0.557 kΩ
  • 0x8B = 0.553 kΩ
  • 0x8C = 0.55 kΩ
  • 0x8D = 0.546 kΩ
  • 0x8E = 0.542 kΩ
  • 0x8F = 0.538 kΩ
  • 0x90 = 0.535 kΩ
  • 0x91 = 0.531 kΩ
  • 0x92 = 0.527 kΩ
  • 0x93 = 0.524 kΩ
  • 0x94 = 0.521 kΩ
  • 0x95 = 0.517 kΩ
  • 0x96 = 0.514 kΩ
  • 0x97 = 0.51 kΩ
  • 0x98 = 0.507 kΩ
  • 0x99 = 0.504 kΩ
  • 0x9A = 0.5 kΩ
  • 0x9B = 0.497 kΩ
  • 0x9C = 0.494 kΩ
  • 0x9D = 0.491 kΩ
  • 0x9E = 0.488 kΩ
  • 0x9F = 0.485 kΩ
  • 0xA0 = 0.48 kΩ
  • 0xA1 = 0.477 kΩ
  • 0xA2 = 0.474 kΩ
  • 0xA3 = 0.471 kΩ
  • 0xA4 = 0.469 kΩ
  • 0xA5 = 0.466 kΩ
  • 0xA6 = 0.463 kΩ
  • 0xA7 = 0.46 kΩ
  • 0xA8 = 0.458 kΩ
  • 0xA9 = 0.455 kΩ
  • 0xAA = 0.452 kΩ
  • 0xAB = 0.45 kΩ
  • 0xAC = 0.447 kΩ
  • 0xAD = 0.445 kΩ
  • 0xAE = 0.442 kΩ
  • 0xAF = 0.44 kΩ
  • 0xB0 = 0.437 kΩ
  • 0xB1 = 0.435 kΩ
  • 0xB2 = 0.432 kΩ
  • 0xB3 = 0.43 kΩ
  • 0xB4 = 0.428 kΩ
  • 0xB5 = 0.425 kΩ
  • 0xB6 = 0.423 kΩ
  • 0xB7 = 0.421 kΩ
  • 0xB8 = 0.419 kΩ
  • 0xB9 = 0.416 kΩ
  • 0xBA = 0.414 kΩ
  • 0xBB = 0.412 kΩ
  • 0xBC = 0.41 kΩ
  • 0xBD = 0.408 kΩ
  • 0xBE = 0.406 kΩ
  • 0xBF = 0.404 kΩ
  • 0xC0 = 0.4 kΩ
  • 0xC1 = 0.398 kΩ
  • 0xC2 = 0.396 kΩ
  • 0xC3 = 0.394 kΩ
  • 0xC4 = 0.392 kΩ
  • 0xC5 = 0.39 kΩ
  • 0xC6 = 0.388 kΩ
  • 0xC7 = 0.386 kΩ
  • 0xC8 = 0.384 kΩ
  • 0xC9 = 0.382 kΩ
  • 0xCA = 0.381 kΩ
  • 0xCB = 0.379 kΩ
  • 0xCC = 0.377 kΩ
  • 0xCD = 0.375 kΩ
  • 0xCE = 0.373 kΩ
  • 0xCF = 0.372 kΩ
  • 0xD0 = 0.37 kΩ
  • 0xD1 = 0.368 kΩ
  • 0xD2 = 0.366 kΩ
  • 0xD3 = 0.365 kΩ
  • 0xD4 = 0.363 kΩ
  • 0xD5 = 0.361 kΩ
  • 0xD6 = 0.36 kΩ
  • 0xD7 = 0.358 kΩ
  • 0xD8 = 0.356 kΩ
  • 0xD9 = 0.355 kΩ
  • 0xDA = 0.353 kΩ
  • 0xDB = 0.352 kΩ
  • 0xDC = 0.35 kΩ
  • 0xDD = 0.349 kΩ
  • 0xDE = 0.347 kΩ
  • 0xDF = 0.345 kΩ
  • 0xE0 = 0.343 kΩ
  • 0xE1 = 0.341 kΩ
  • 0xE2 = 0.34 kΩ
  • 0xE3 = 0.338 kΩ
  • 0xE4 = 0.337 kΩ
  • 0xE5 = 0.336 kΩ
  • 0xE6 = 0.334 kΩ
  • 0xE7 = 0.333 kΩ
  • 0xE8 = 0.331 kΩ
  • 0xE9 = 0.33 kΩ
  • 0xEA = 0.328 kΩ
  • 0xEB = 0.327 kΩ
  • 0xEC = 0.326 kΩ
  • 0xED = 0.325 kΩ
  • 0xEE = 0.323 kΩ
  • 0xEF = 0.322 kΩ
  • 0xF0 = 0.32 kΩ
  • 0xF1 = 0.319 kΩ
  • 0xF2 = 0.318 kΩ
  • 0xF3 = 0.317 kΩ
  • 0xF4 = 0.315 kΩ
  • 0xF5 = 0.314 kΩ
  • 0xF6 = 0.313 kΩ
  • 0xF7 = 0.312 kΩ
  • 0xF8 = 0.31 kΩ
  • 0xF9 = 0.309 kΩ
  • 0xFA = 0.308 kΩ
  • 0xFB = 0.307 kΩ
  • 0xFC = 0.306 kΩ
  • 0xFD = 0.304 kΩ
  • 0xFE = 0.303 kΩ
  • 0xFF = 0.302 kΩ

1.505 R778 (Offset = 0x30A)

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Table 1-507 R778 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4PLL2_CP_PU_DISR/W0x0 PLL charge pump - pump up disable
ROM=Y, EEPROM=N
3:0PLL2_CPGR/W0x3 PLL charge pump gain
ROM=Y, EEPROM=Y
  • 0x0 = 0 mA
  • 0x1 = 0.4 mA
  • 0x2 = 0.8 mA
  • 0x3 = 1.2 mA
  • 0x4 = 1.6 mA
  • 0x5 = 2.0 mA
  • 0x6 = 2.4 mA
  • 0x7 = 2.8 mA
  • 0x8 = 3.0 mA
  • 0x9 = 3.4 mA
  • 0xA = 3.8 mA
  • 0xB = 4.2 mA
  • 0xC = 4.6 mA
  • 0xD = 5.0 mA
  • 0xE = 5.4 mA
  • 0xF = 5.8 mA

1.506 R779 (Offset = 0x30B)

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Table 1-508 R779 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_LF_R2R/W0x0 PLL Loop Filter R2 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.301 kΩ
  • 0x2 = 0.551 kΩ
  • 0x3 = 0.209 kΩ
  • 0x4 = 1.05 kΩ
  • 0x5 = 0.244 kΩ
  • 0x6 = 0.375 kΩ
  • 0x7 = 0.183 kΩ
  • 0x8 = 2.05 kΩ
  • 0x9 = 0.269 kΩ
  • 0xA = 0.444 kΩ
  • 0xB = 0.194 kΩ
  • 0xC = 0.709 kΩ
  • 0xD = 0.224 kΩ
  • 0xE = 0.0446 kΩ
  • 0xF = 0.0421 kΩ
  • 0x10 = 0.932 kΩ
  • 0x11 = 1.18 kΩ
  • 0x12 = 1.43 kΩ
  • 0x13 = 1.09 kΩ
  • 0x14 = 1.93 kΩ
  • 0x15 = 1.13 kΩ
  • 0x16 = 1.26 kΩ
  • 0x17 = 1.07 kΩ
  • 0x18 = 2.93 kΩ
  • 0x19 = 1.15 kΩ
  • 0x1A = 1.33 kΩ
  • 0x1B = 1.08 kΩ
  • 0x1C = 1.59 kΩ
  • 0x1D = 1.11 kΩ
  • 0x1E = 0.929 kΩ
  • 0x1F = 0.926 kΩ
  • 0x20 = 1.83 kΩ
  • 0x21 = 2.08 kΩ
  • 0x22 = 2.33 kΩ
  • 0x23 = 1.99 kΩ
  • 0x24 = 2.83 kΩ
  • 0x25 = 2.03 kΩ
  • 0x26 = 2.16 kΩ
  • 0x27 = 1.97 kΩ
  • 0x28 = 3.83 kΩ
  • 0x29 = 2.05 kΩ
  • 0x2A = 2.23 kΩ
  • 0x2B = 1.98 kΩ
  • 0x2C = 2.49 kΩ
  • 0x2D = 2.01 kΩ
  • 0x2E = 1.83 kΩ
  • 0x2F = 1.83 kΩ
  • 0x30 = 2.72 kΩ
  • 0x31 = 2.97 kΩ
  • 0x32 = 3.22 kΩ
  • 0x33 = 2.88 kΩ
  • 0x34 = 3.72 kΩ
  • 0x35 = 2.91 kΩ
  • 0x36 = 3.04 kΩ
  • 0x37 = 2.85 kΩ
  • 0x38 = 4.72 kΩ
  • 0x39 = 2.94 kΩ
  • 0x3A = 3.11 kΩ
  • 0x3B = 2.86 kΩ
  • 0x3C = 3.38 kΩ
  • 0x3D = 2.89 kΩ
  • 0x3E = 2.71 kΩ
  • 0x3F = 2.71 kΩ

1.507 R780 (Offset = 0x30C)

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Table 1-509 R780 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL2_LF_R3R/W0x0 PLL Loop Filter R3 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.277 kΩ
  • 0x2 = 0.657 kΩ
  • 0x3 = 0.214 kΩ
  • 0x4 = 0.754 kΩ
  • 0x5 = 0.221 kΩ
  • 0x6 = 0.375 kΩ
  • 0x7 = 0.183 kΩ
  • 0x8 = 0.863 kΩ
  • 0x9 = 1.08 kΩ
  • 0xA = 1.46 kΩ
  • 0xB = 1.01 kΩ
  • 0xC = 1.55 kΩ
  • 0xD = 1.02 kΩ
  • 0xE = 1.17 kΩ
  • 0xF = 0.982 kΩ
  • 0x10 = 1.68 kΩ
  • 0x11 = 1.89 kΩ
  • 0x12 = 2.27 kΩ
  • 0x13 = 1.83 kΩ
  • 0x14 = 2.37 kΩ
  • 0x15 = 1.84 kΩ
  • 0x16 = 1.99 kΩ
  • 0x17 = 1.8 kΩ
  • 0x18 = 2.48 kΩ
  • 0x19 = 2.69 kΩ
  • 0x1A = 3.07 kΩ
  • 0x1B = 2.63 kΩ
  • 0x1C = 3.17 kΩ
  • 0x1D = 2.63 kΩ
  • 0x1E = 2.79 kΩ
  • 0x1F = 2.6 kΩ
  • 0x20 = 3.31 kΩ
  • 0x21 = 3.52 kΩ
  • 0x22 = 3.9 kΩ
  • 0x23 = 3.46 kΩ
  • 0x24 = 4 kΩ
  • 0x25 = 3.47 kΩ
  • 0x26 = 3.62 kΩ
  • 0x27 = 3.43 kΩ
  • 0x28 = 4.11 kΩ
  • 0x29 = 4.32 kΩ
  • 0x2A = 4.7 kΩ
  • 0x2B = 4.26 kΩ
  • 0x2C = 4.8 kΩ
  • 0x2D = 4.26 kΩ
  • 0x2E = 4.42 kΩ
  • 0x2F = 4.23 kΩ
  • 0x30 = 4.92 kΩ
  • 0x31 = 5.14 kΩ
  • 0x32 = 5.52 kΩ
  • 0x33 = 5.07 kΩ
  • 0x34 = 5.61 kΩ
  • 0x35 = 5.08 kΩ
  • 0x36 = 5.23 kΩ
  • 0x37 = 5.04 kΩ
  • 0x38 = 5.72 kΩ
  • 0x39 = 5.94 kΩ
  • 0x3A = 6.32 kΩ
  • 0x3B = 5.87 kΩ
  • 0x3C = 6.41 kΩ
  • 0x3D = 5.88 kΩ
  • 0x3E = 6.03 kΩ
  • 0x3F = 5.84 kΩ

1.508 R781 (Offset = 0x30D)

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Table 1-510 R781 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL2_LF_R4R/W0x0 PLL Loop Filter R4 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.277 kΩ
  • 0x2 = 0.657 kΩ
  • 0x3 = 0.214 kΩ
  • 0x4 = 0.754 kΩ
  • 0x5 = 0.221 kΩ
  • 0x6 = 0.375 kΩ
  • 0x7 = 0.183 kΩ
  • 0x8 = 0.863 kΩ
  • 0x9 = 1.08 kΩ
  • 0xA = 1.46 kΩ
  • 0xB = 1.01 kΩ
  • 0xC = 1.55 kΩ
  • 0xD = 1.02 kΩ
  • 0xE = 1.17 kΩ
  • 0xF = 0.982 kΩ
  • 0x10 = 1.68 kΩ
  • 0x11 = 1.89 kΩ
  • 0x12 = 2.27 kΩ
  • 0x13 = 1.83 kΩ
  • 0x14 = 2.37 kΩ
  • 0x15 = 1.84 kΩ
  • 0x16 = 1.99 kΩ
  • 0x17 = 1.8 kΩ
  • 0x18 = 2.48 kΩ
  • 0x19 = 2.69 kΩ
  • 0x1A = 3.07 kΩ
  • 0x1B = 2.63 kΩ
  • 0x1C = 3.17 kΩ
  • 0x1D = 2.63 kΩ
  • 0x1E = 2.79 kΩ
  • 0x1F = 2.6 kΩ
  • 0x20 = 3.31 kΩ
  • 0x21 = 3.52 kΩ
  • 0x22 = 3.9 kΩ
  • 0x23 = 3.46 kΩ
  • 0x24 = 4 kΩ
  • 0x25 = 3.47 kΩ
  • 0x26 = 3.62 kΩ
  • 0x27 = 3.43 kΩ
  • 0x28 = 4.11 kΩ
  • 0x29 = 4.32 kΩ
  • 0x2A = 4.7 kΩ
  • 0x2B = 4.26 kΩ
  • 0x2C = 4.8 kΩ
  • 0x2D = 4.26 kΩ
  • 0x2E = 4.42 kΩ
  • 0x2F = 4.23 kΩ
  • 0x30 = 4.92 kΩ
  • 0x31 = 5.14 kΩ
  • 0x32 = 5.52 kΩ
  • 0x33 = 5.07 kΩ
  • 0x34 = 5.61 kΩ
  • 0x35 = 5.08 kΩ
  • 0x36 = 5.23 kΩ
  • 0x37 = 5.04 kΩ
  • 0x38 = 5.72 kΩ
  • 0x39 = 5.94 kΩ
  • 0x3A = 6.32 kΩ
  • 0x3B = 5.87 kΩ
  • 0x3C = 6.41 kΩ
  • 0x3D = 5.88 kΩ
  • 0x3E = 6.03 kΩ
  • 0x3F = 5.84 kΩ

1.509 R782 (Offset = 0x30E)

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Table 1-511 R782 Field Descriptions
BitFieldTypeResetDescription
7:6PLL2_DISABLE_3RD4THR/W0x0 PLL Loop Filter Disconnects C3 and C4
ROM=Y, EEPROM=N
  • 0x0 = C3/C4 Disconnected
  • 0x1 = C3=Enabled, C4=Disconnected
  • 0x2 = C3=Disconnected, C4=Enabled
  • 0x3 = C3=Enabled, C4=Enabled
5:3PLL2_LF_C3R/W0x0 PLL Loop Filter C3 setting
ROM=Y, EEPROM=N
  • 0x0 = 0 pF
  • 0x1 = 10 pF
  • 0x2 = 20 pF
  • 0x3 = 30 pF
  • 0x4 = 40 pF
  • 0x5 = 50 pF
  • 0x6 = 60 pF
  • 0x7 = 70 pF
2:0PLL2_LF_C4R/W0x0 PLL Loop Filter C4 setting
ROM=Y, EEPROM=N
  • 0x0 = 0 pF
  • 0x1 = 10 pF
  • 0x2 = 20 pF
  • 0x3 = 30 pF
  • 0x4 = 40 pF
  • 0x5 = 50 pF
  • 0x6 = 60 pF
  • 0x7 = 70 pF

1.510 R783 (Offset = 0x30F)

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Table 1-512 R783 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL2_RDIV_8:8R/W0x0 See Register 784

1.511 R784 (Offset = 0x310)

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Table 1-513 R784 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_RDIVR/W0x1 PLL R Divider
ROM=Y, EEPROM=Y

1.512 R785 (Offset = 0x311)

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Table 1-514 R785 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4PLL2_RDIV_XO_ENR/W0x0 APLL reference source is from XO. Must also enable XO to drive this APLL with XO_OUT_BUF_EN[2] = 1
ROM=Y, EEPROM=Y
3PLL2_RDIV_XO_DBLR_ENR/W0x0 Enables XO Doubler
ROM=Y, EEPROM=Y
2PLL2_RDIV_BYPASS_ENR/W0x0 Bypass R Divider
ROM=Y, EEPROM=Y
1:0PLL2_RDIV_MUX_SELR/W0x0 Select R Divider input: 0=XO, 1=VCO1 feedback divider, 2=VCO3 feedback divider
ROM=Y, EEPROM=Y
  • 0x0 = XO
  • 0x1 = VCO1 feedback divider
  • 0x2 = VCO3 feedback divider

1.513 R786 (Offset = 0x312)

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Table 1-515 R786 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL2_NDIV_8:8R/W0x0 See Register 787

1.514 R787 (Offset = 0x313)

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Table 1-516 R787 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NDIVR/W0x4D PLL N Divider
ROM=Y, EEPROM=Y

1.515 R788 (Offset = 0x314)

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Table 1-517 R788 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NUM_MSBR/W0x29 When PLL2_MODE is set for 24 bit fractional. PLL2_NUM_MSB is effective PLL2_NUM[23:16]. Other PLL2_NUM and PLL2_DEN bits in programmable mode are in PLL2_NUM field. When in 40-bit fixed denominator PLL mode, then PLL2_NUM_MSB is unused.
ROM=Y, EEPROM=Y

1.516 R789 (Offset = 0x315)

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Table 1-518 R789 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NUM_39:32R/W0x29 See Register 793

1.517 R790 (Offset = 0x316)

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Table 1-519 R790 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NUM_31:24R/W0x16 See Register 793

1.518 R791 (Offset = 0x317)

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Table 1-520 R791 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NUM_23:16R/W0x1F See Register 793

1.519 R792 (Offset = 0x318)

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Table 1-521 R792 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NUM_15:8R/W0x9A See Register 793

1.520 R793 (Offset = 0x319)

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Table 1-522 R793 Field Descriptions
BitFieldTypeResetDescription
7:0PLL2_NUMR/W0xDD When PLL2_MODE = 1 (40-bit fixed denominator) mode then PLL2_NUM contains the APLL2 numerator. When PLL2_MODE = 0 (24-bit programmable denominator) then PLL2_NUM[23:0] stores the programmable PLL2 denominator and PLL2_NUM[39:24] stores the 16 LSBs of the PLL2 numerator. Total PLL2 numerator is calculated with PLL2_NUM_MSB as the 8 MSBs. In 24-bit programmable denominator mode PLL2_NUM[23:0] = 0 is 224.
ROM=Y, EEPROM=Y

1.521 R794 (Offset = 0x31A)

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Table 1-523 R794 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:4PLL2_DTHRMODER/W0x0 PLL MASH Dither Mode
ROM=Y, EEPROM=N
  • 0x0 = Constant Dither MACC2
  • 0x1 = Constant Dither MACC2 and MACC3
  • 0x2 = LFSR Dither MACC2
  • 0x3 = Dither Disabled
3:1PLL2_ORDERR/W0x0 PLL MASH Order
ROM=Y, EEPROM=N
  • 0x0 = Integer Mode Divider
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
0PLL2_MODER/W0x0 In APLL 24-bit num/den mode, APLL denominator is programmable. Not for use with DPLL mode. In 24-bit mode, the denominator is stored in PLL2_NUM[23:0] The numerator is stored in (PLL2_NUM_MSB << 16) + PLL2_NUM[39:24].

In APLL 40-bit mode, APLL denominator is fixed. For use with DPLL.
ROM=Y, EEPROM=Y
  • 0x0 = APLL 24-bit num/den
  • 0x1 = APLL 40-bit num (Req for DPLL)

1.522 R795 (Offset = 0x31B)

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Table 1-524 R795 Field Descriptions
BitFieldTypeResetDescription
7:0APLL2_NUM_STAT_39:32R0x0 See Register 799

1.523 R796 (Offset = 0x31C)

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Table 1-525 R796 Field Descriptions
BitFieldTypeResetDescription
7:0APLL2_NUM_STAT_31:24R0x0 See Register 799

1.524 R797 (Offset = 0x31D)

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Table 1-526 R797 Field Descriptions
BitFieldTypeResetDescription
7:0APLL2_NUM_STAT_23:16R0x0 See Register 799

1.525 R798 (Offset = 0x31E)

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Table 1-527 R798 Field Descriptions
BitFieldTypeResetDescription
7:0APLL2_NUM_STAT_15:8R0x0 See Register 799

1.526 R799 (Offset = 0x31F)

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Table 1-528 R799 Field Descriptions
BitFieldTypeResetDescription
7:0APLL2_NUM_STATR0x0 Readback current effective APLL2 Numerator after FDEV and/or DPLL correction
ROM=N, EEPROM=N

1.527 R803 (Offset = 0x323)

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Table 1-529 R803 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:5RESERVEDR0x0 Reserved
4PLL2_VCO_BUF_ENR/W0x0 Enables the VCO2 Buffer which drives the DPLL feedback, reference window detector, DPLL reference for cascade mode, and test mode
ROM=Y, EEPROM=N
3:2PLL2_VCO_BUF_2REF_ENR/W0x0 Enables the APLL2 Div-by-4 cascade divider to [0] -> APLL1 and [1] -> APLL3 reference input for cascade mode.
ROM=Y, EEPROM=Y
1PLL2_VCO_BUF_2DPLL_ENR/W0x0 Enables the VCO2 Buffer output driver to DPLL2 feedback divider
ROM=Y, EEPROM=N
0PLL2_VCO_BUF_2WNDDET_ENR/W0x0 Enables the APLL2 Div-by-5 cascade divider to reference window detectors input buffer and prepares pre-divided clock for DPLL2 loop filter and PPM/Frequency detector.
ROM=Y, EEPROM=N

1.528 R804 (Offset = 0x324)

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Table 1-530 R804 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5PLL2_VCO_DIV_SYNC_ENR/W0x0 PLL2 Divider Sync Enable. Enables synchronization of post-dividers and reference dividers for PLL2.
ROM=Y, EEPROM=N
4PLL2_VCO_DIV_ENR/W0x0 Enables the VCO2 Div By 2 to 13 divide block.
ROM=Y, EEPROM=Y
3:0PLL2_VCO_DIVR/W0x1 Sets the VCO2 divider divide value from 2 to 13
ROM=Y, EEPROM=Y
  • 0x0 = 2 (Reserved)
  • 0x1 = 2 (Reserved)
  • 0x2 = 2
  • 0x3 = 3
  • 0x4 = 4
  • 0x5 = 5
  • 0x6 = 6
  • 0x7 = 7
  • 0x8 = 8
  • 0x9 = 9
  • 0xA = 10
  • 0xB = 11
  • 0xC = 12
  • 0xD = 13

1.529 R805 (Offset = 0x325)

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Table 1-531 R805 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:5PLL2_VCO_BUF_FB_TDC_ENR/W0x0 Enables APLL2 Div-by-10 cascade divider to TDC1 and TDC3 for cascade mode [0] = TDC1 driver enable [1] = TDC3 driver enable
ROM=Y, EEPROM=N
4PLL2_P1_OUT14_15_ENR/W0x0 Enable VCO2 P1 divider output driver to channel output bank OUT14_15
ROM=Y, EEPROM=Y
3PLL2_P1_OUT8_13_ENR/W0x0 Enable VCO2 P1 divider output driver to channel output bank OUT8_13
ROM=Y, EEPROM=Y
2PLL2_P1_OUT4_7_ENR/W0x0 Enable VCO2 P1 divider output driver to channel output bank OUT4_7
ROM=Y, EEPROM=Y
1PLL2_P1_OUT2_3_ENR/W0x0 Enable VCO2 P1 divider output driver to channel output bank OUT2_3
ROM=Y, EEPROM=Y
0PLL2_P1_OUT0_1_ENR/W0x0 Enable VCO2 P1 divider output driver to channel output bank OUT0_1
ROM=Y, EEPROM=Y

1.530 R808 (Offset = 0x328)

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Table 1-532 R808 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3PLL2_RDIV_OUTPUT_ENR/W0x0 If GPIOx_SEL selects PLL2 R/2 as an output. Then this bit must be set along with STATUS_MUX_DIV2_EN=1.
ROM=N, EEPROM=N
2:0RESERVEDR0x0 Reserved

1.531 R813 (Offset = 0x32D)

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Table 1-533 R813 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5PLL2_VM_INSIDER0x0 Denotes if the VCO tuning voltage is within operational range.
ROM=N, EEPROM=N
4PLL2_VM_HIR0x0 Denotes if the charge pump voltage is too high and outside range. If PLL2_VM_INSIDE = 0 and VM_HI = 0, then charge pump voltage is too low.
ROM=N, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.532 R818 (Offset = 0x332)

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Table 1-534 R818 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5PLL2_NDIV_OUTPUT_ENR/W0x0 If GPIOx_SEL selects PLL2 N/2 as an output. Then this bit must be set along with STATUS_MUX_DIV2_EN=1.
ROM=N, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.533 R819 (Offset = 0x333)

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Table 1-535 R819 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL2_VCO_PREBUF_ENR/W0x0 Set to same value as APLL2_EN.
ROM=Y, EEPROM=Y

1.534 R840 (Offset = 0x348)

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Table 1-536 R840 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_CPBAW_BLEEDR/W0x0 PLL charge pump pull-up resistor selection
ROM=Y, EEPROM=N
  • 0x0 = Disabled
  • 0x1 = 78 kΩ
  • 0x2 = 39 kΩ
  • 0x3 = 26 kΩ
  • 0x4 = 20 kΩ
  • 0x5 = 15.9 kΩ
  • 0x6 = 13.2 kΩ
  • 0x7 = 11.3 kΩ
  • 0x8 = 9.8 kΩ
  • 0x9 = 8.71 kΩ
  • 0xA = 7.83 kΩ
  • 0xB = 7.12 kΩ
  • 0xC = 6.58 kΩ
  • 0xD = 6.07 kΩ
  • 0xE = 5.63 kΩ
  • 0xF = 5.25 kΩ
  • 0x10 = 4.9 kΩ
  • 0x11 = 4.61 kΩ
  • 0x12 = 4.35 kΩ
  • 0x13 = 4.12 kΩ
  • 0x14 = 3.94 kΩ
  • 0x15 = 3.75 kΩ
  • 0x16 = 3.57 kΩ
  • 0x17 = 3.42 kΩ
  • 0x18 = 3.27 kΩ
  • 0x19 = 3.14 kΩ
  • 0x1A = 3.01 kΩ
  • 0x1B = 2.9 kΩ
  • 0x1C = 2.81 kΩ
  • 0x1D = 2.71 kΩ
  • 0x1E = 2.62 kΩ
  • 0x1F = 2.53 kΩ
  • 0x20 = 2.4 kΩ
  • 0x21 = 2.33 kΩ
  • 0x22 = 2.26 kΩ
  • 0x23 = 2.2 kΩ
  • 0x24 = 2.14 kΩ
  • 0x25 = 2.09 kΩ
  • 0x26 = 2.03 kΩ
  • 0x27 = 1.98 kΩ
  • 0x28 = 1.93 kΩ
  • 0x29 = 1.88 kΩ
  • 0x2A = 1.84 kΩ
  • 0x2B = 1.79 kΩ
  • 0x2C = 1.76 kΩ
  • 0x2D = 1.72 kΩ
  • 0x2E = 1.68 kΩ
  • 0x2F = 1.65 kΩ
  • 0x30 = 1.61 kΩ
  • 0x31 = 1.58 kΩ
  • 0x32 = 1.55 kΩ
  • 0x33 = 1.52 kΩ
  • 0x34 = 1.49 kΩ
  • 0x35 = 1.46 kΩ
  • 0x36 = 1.44 kΩ
  • 0x37 = 1.41 kΩ
  • 0x38 = 1.38 kΩ
  • 0x39 = 1.36 kΩ
  • 0x3A = 1.34 kΩ
  • 0x3B = 1.31 kΩ
  • 0x3C = 1.29 kΩ
  • 0x3D = 1.27 kΩ
  • 0x3E = 1.25 kΩ
  • 0x3F = 1.23 kΩ
  • 0x40 = 1.2 kΩ
  • 0x41 = 1.18 kΩ
  • 0x42 = 1.16 kΩ
  • 0x43 = 1.15 kΩ
  • 0x44 = 1.13 kΩ
  • 0x45 = 1.12 kΩ
  • 0x46 = 1.1 kΩ
  • 0x47 = 1.08 kΩ
  • 0x48 = 1.07 kΩ
  • 0x49 = 1.05 kΩ
  • 0x4A = 1.04 kΩ
  • 0x4B = 1.03 kΩ
  • 0x4C = 1.01 kΩ
  • 0x4D = 1 kΩ
  • 0x4E = 0.989 kΩ
  • 0x4F = 0.977 kΩ
  • 0x50 = 0.964 kΩ
  • 0x51 = 0.952 kΩ
  • 0x52 = 0.941 kΩ
  • 0x53 = 0.929 kΩ
  • 0x54 = 0.92 kΩ
  • 0x55 = 0.909 kΩ
  • 0x56 = 0.898 kΩ
  • 0x57 = 0.888 kΩ
  • 0x58 = 0.878 kΩ
  • 0x59 = 0.868 kΩ
  • 0x5A = 0.858 kΩ
  • 0x5B = 0.849 kΩ
  • 0x5C = 0.841 kΩ
  • 0x5D = 0.832 kΩ
  • 0x5E = 0.823 kΩ
  • 0x5F = 0.814 kΩ
  • 0x60 = 0.8 kΩ
  • 0x61 = 0.792 kΩ
  • 0x62 = 0.784 kΩ
  • 0x63 = 0.776 kΩ
  • 0x64 = 0.769 kΩ
  • 0x65 = 0.762 kΩ
  • 0x66 = 0.754 kΩ
  • 0x67 = 0.747 kΩ
  • 0x68 = 0.74 kΩ
  • 0x69 = 0.733 kΩ
  • 0x6A = 0.726 kΩ
  • 0x6B = 0.719 kΩ
  • 0x6C = 0.713 kΩ
  • 0x6D = 0.707 kΩ
  • 0x6E = 0.7 kΩ
  • 0x6F = 0.694 kΩ
  • 0x70 = 0.688 kΩ
  • 0x71 = 0.682 kΩ
  • 0x72 = 0.676 kΩ
  • 0x73 = 0.67 kΩ
  • 0x74 = 0.665 kΩ
  • 0x75 = 0.659 kΩ
  • 0x76 = 0.654 kΩ
  • 0x77 = 0.648 kΩ
  • 0x78 = 0.643 kΩ
  • 0x79 = 0.637 kΩ
  • 0x7A = 0.632 kΩ
  • 0x7B = 0.627 kΩ
  • 0x7C = 0.623 kΩ
  • 0x7D = 0.618 kΩ
  • 0x7E = 0.613 kΩ
  • 0x7F = 0.608 kΩ
  • 0x80 = 0.6 kΩ
  • 0x81 = 0.595 kΩ
  • 0x82 = 0.591 kΩ
  • 0x83 = 0.586 kΩ
  • 0x84 = 0.583 kΩ
  • 0x85 = 0.578 kΩ
  • 0x86 = 0.574 kΩ
  • 0x87 = 0.57 kΩ
  • 0x88 = 0.565 kΩ
  • 0x89 = 0.561 kΩ
  • 0x8A = 0.557 kΩ
  • 0x8B = 0.553 kΩ
  • 0x8C = 0.55 kΩ
  • 0x8D = 0.546 kΩ
  • 0x8E = 0.542 kΩ
  • 0x8F = 0.538 kΩ
  • 0x90 = 0.535 kΩ
  • 0x91 = 0.531 kΩ
  • 0x92 = 0.527 kΩ
  • 0x93 = 0.524 kΩ
  • 0x94 = 0.521 kΩ
  • 0x95 = 0.517 kΩ
  • 0x96 = 0.514 kΩ
  • 0x97 = 0.51 kΩ
  • 0x98 = 0.507 kΩ
  • 0x99 = 0.504 kΩ
  • 0x9A = 0.5 kΩ
  • 0x9B = 0.497 kΩ
  • 0x9C = 0.494 kΩ
  • 0x9D = 0.491 kΩ
  • 0x9E = 0.488 kΩ
  • 0x9F = 0.485 kΩ
  • 0xA0 = 0.48 kΩ
  • 0xA1 = 0.477 kΩ
  • 0xA2 = 0.474 kΩ
  • 0xA3 = 0.471 kΩ
  • 0xA4 = 0.469 kΩ
  • 0xA5 = 0.466 kΩ
  • 0xA6 = 0.463 kΩ
  • 0xA7 = 0.46 kΩ
  • 0xA8 = 0.458 kΩ
  • 0xA9 = 0.455 kΩ
  • 0xAA = 0.452 kΩ
  • 0xAB = 0.45 kΩ
  • 0xAC = 0.447 kΩ
  • 0xAD = 0.445 kΩ
  • 0xAE = 0.442 kΩ
  • 0xAF = 0.44 kΩ
  • 0xB0 = 0.437 kΩ
  • 0xB1 = 0.435 kΩ
  • 0xB2 = 0.432 kΩ
  • 0xB3 = 0.43 kΩ
  • 0xB4 = 0.428 kΩ
  • 0xB5 = 0.425 kΩ
  • 0xB6 = 0.423 kΩ
  • 0xB7 = 0.421 kΩ
  • 0xB8 = 0.419 kΩ
  • 0xB9 = 0.416 kΩ
  • 0xBA = 0.414 kΩ
  • 0xBB = 0.412 kΩ
  • 0xBC = 0.41 kΩ
  • 0xBD = 0.408 kΩ
  • 0xBE = 0.406 kΩ
  • 0xBF = 0.404 kΩ
  • 0xC0 = 0.4 kΩ
  • 0xC1 = 0.398 kΩ
  • 0xC2 = 0.396 kΩ
  • 0xC3 = 0.394 kΩ
  • 0xC4 = 0.392 kΩ
  • 0xC5 = 0.39 kΩ
  • 0xC6 = 0.388 kΩ
  • 0xC7 = 0.386 kΩ
  • 0xC8 = 0.384 kΩ
  • 0xC9 = 0.382 kΩ
  • 0xCA = 0.381 kΩ
  • 0xCB = 0.379 kΩ
  • 0xCC = 0.377 kΩ
  • 0xCD = 0.375 kΩ
  • 0xCE = 0.373 kΩ
  • 0xCF = 0.372 kΩ
  • 0xD0 = 0.37 kΩ
  • 0xD1 = 0.368 kΩ
  • 0xD2 = 0.366 kΩ
  • 0xD3 = 0.365 kΩ
  • 0xD4 = 0.363 kΩ
  • 0xD5 = 0.361 kΩ
  • 0xD6 = 0.36 kΩ
  • 0xD7 = 0.358 kΩ
  • 0xD8 = 0.356 kΩ
  • 0xD9 = 0.355 kΩ
  • 0xDA = 0.353 kΩ
  • 0xDB = 0.352 kΩ
  • 0xDC = 0.35 kΩ
  • 0xDD = 0.349 kΩ
  • 0xDE = 0.347 kΩ
  • 0xDF = 0.345 kΩ
  • 0xE0 = 0.343 kΩ
  • 0xE1 = 0.341 kΩ
  • 0xE2 = 0.34 kΩ
  • 0xE3 = 0.338 kΩ
  • 0xE4 = 0.337 kΩ
  • 0xE5 = 0.336 kΩ
  • 0xE6 = 0.334 kΩ
  • 0xE7 = 0.333 kΩ
  • 0xE8 = 0.331 kΩ
  • 0xE9 = 0.33 kΩ
  • 0xEA = 0.328 kΩ
  • 0xEB = 0.327 kΩ
  • 0xEC = 0.326 kΩ
  • 0xED = 0.325 kΩ
  • 0xEE = 0.323 kΩ
  • 0xEF = 0.322 kΩ
  • 0xF0 = 0.32 kΩ
  • 0xF1 = 0.319 kΩ
  • 0xF2 = 0.318 kΩ
  • 0xF3 = 0.317 kΩ
  • 0xF4 = 0.315 kΩ
  • 0xF5 = 0.314 kΩ
  • 0xF6 = 0.313 kΩ
  • 0xF7 = 0.312 kΩ
  • 0xF8 = 0.31 kΩ
  • 0xF9 = 0.309 kΩ
  • 0xFA = 0.308 kΩ
  • 0xFB = 0.307 kΩ
  • 0xFC = 0.306 kΩ
  • 0xFD = 0.304 kΩ
  • 0xFE = 0.303 kΩ
  • 0xFF = 0.302 kΩ

1.535 R841 (Offset = 0x349)

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Table 1-537 R841 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4PLL3_CP_PU_DISR/W0x0 PLL charge pump pump-up disable
ROM=Y, EEPROM=N
3:0PLL3_CPGR/W0x0 PLL charge pump gain
ROM=Y, EEPROM=N
  • 0x0 = 0 mA
  • 0x1 = 0.4 mA
  • 0x2 = 0.8 mA
  • 0x3 = 1.2 mA
  • 0x4 = 1.6 mA
  • 0x5 = 2.0 mA
  • 0x6 = 2.4 mA
  • 0x7 = 2.8 mA
  • 0x8 = 3.0 mA
  • 0x9 = 3.4 mA
  • 0xA = 3.8 mA
  • 0xB = 4.2 mA
  • 0xC = 4.6 mA
  • 0xD = 5.0 mA
  • 0xE = 5.4 mA
  • 0xF = 5.8 mA

1.536 R842 (Offset = 0x34A)

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Table 1-538 R842 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL3_LF_R2R/W0x0 PLL Loop Filter R2 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.016 kΩ
  • 0x1 = 0.301 kΩ
  • 0x2 = 0.551 kΩ
  • 0x3 = 0.209 kΩ
  • 0x4 = 1.05 kΩ
  • 0x5 = 0.244 kΩ
  • 0x6 = 0.375 kΩ
  • 0x7 = 0.183 kΩ
  • 0x8 = 2.05 kΩ
  • 0x9 = 0.269 kΩ
  • 0xA = 0.444 kΩ
  • 0xB = 0.194 kΩ
  • 0xC = 0.709 kΩ
  • 0xD = 0.224 kΩ
  • 0xE = 0.0446 kΩ
  • 0xF = 0.0421 kΩ
  • 0x10 = 0.932 kΩ
  • 0x11 = 1.18 kΩ
  • 0x12 = 1.43 kΩ
  • 0x13 = 1.09 kΩ
  • 0x14 = 1.93 kΩ
  • 0x15 = 1.13 kΩ
  • 0x16 = 1.26 kΩ
  • 0x17 = 1.07 kΩ
  • 0x18 = 2.93 kΩ
  • 0x19 = 1.15 kΩ
  • 0x1A = 1.33 kΩ
  • 0x1B = 1.08 kΩ
  • 0x1C = 1.59 kΩ
  • 0x1D = 1.11 kΩ
  • 0x1E = 0.929 kΩ
  • 0x1F = 0.926 kΩ
  • 0x20 = 1.83 kΩ
  • 0x21 = 2.08 kΩ
  • 0x22 = 2.33 kΩ
  • 0x23 = 1.99 kΩ
  • 0x24 = 2.83 kΩ
  • 0x25 = 2.03 kΩ
  • 0x26 = 2.16 kΩ
  • 0x27 = 1.97 kΩ
  • 0x28 = 3.83 kΩ
  • 0x29 = 2.05 kΩ
  • 0x2A = 2.23 kΩ
  • 0x2B = 1.98 kΩ
  • 0x2C = 2.49 kΩ
  • 0x2D = 2.01 kΩ
  • 0x2E = 1.83 kΩ
  • 0x2F = 1.83 kΩ
  • 0x30 = 2.72 kΩ
  • 0x31 = 2.97 kΩ
  • 0x32 = 3.22 kΩ
  • 0x33 = 2.88 kΩ
  • 0x34 = 3.72 kΩ
  • 0x35 = 2.91 kΩ
  • 0x36 = 3.04 kΩ
  • 0x37 = 2.85 kΩ
  • 0x38 = 4.72 kΩ
  • 0x39 = 2.94 kΩ
  • 0x3A = 3.11 kΩ
  • 0x3B = 2.86 kΩ
  • 0x3C = 3.38 kΩ
  • 0x3D = 2.89 kΩ
  • 0x3E = 2.71 kΩ
  • 0x3F = 2.71 kΩ

1.537 R843 (Offset = 0x34B)

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Table 1-539 R843 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL3_LF_R3R/W0x0 PLL Loop Filter R3 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.0139 kΩ
  • 0x1 = 0.51 kΩ
  • 0x2 = 0.826 kΩ
  • 0x3 = 1.23 kΩ
  • 0x4 = 1.85 kΩ
  • 0x5 = 2.26 kΩ
  • 0x6 = 2.57 kΩ
  • 0x7 = 2.97 kΩ
  • 0x8 = 3.3 kΩ
  • 0x9 = 3.75 kΩ
  • 0xA = 4.07 kΩ
  • 0xB = 4.47 kΩ
  • 0xC = 5.09 kΩ
  • 0xD = 5.5 kΩ
  • 0xE = 5.81 kΩ
  • 0xF = 6.22 kΩ
  • 0x10 = 6.57 kΩ
  • 0x11 = 7.01 kΩ
  • 0x12 = 7.33 kΩ
  • 0x13 = 7.73 kΩ
  • 0x14 = 8.36 kΩ
  • 0x15 = 8.76 kΩ
  • 0x16 = 9.08 kΩ
  • 0x17 = 9.48 kΩ
  • 0x18 = 9.81 kΩ
  • 0x19 = 10.3 kΩ
  • 0x1A = 10.6 kΩ
  • 0x1B = 11 kΩ
  • 0x1C = 11.6 kΩ
  • 0x1D = 12 kΩ
  • 0x1E = 12.3 kΩ
  • 0x1F = 12.7 kΩ
  • 0x20 = 13 kΩ
  • 0x21 = 13.5 kΩ
  • 0x22 = 13.8 kΩ
  • 0x23 = 14.2 kΩ
  • 0x24 = 14.8 kΩ
  • 0x25 = 15.2 kΩ
  • 0x26 = 15.6 kΩ
  • 0x27 = 16 kΩ
  • 0x28 = 16.3 kΩ
  • 0x29 = 16.7 kΩ
  • 0x2A = 17.1 kΩ
  • 0x2B = 17.5 kΩ
  • 0x2C = 18.1 kΩ
  • 0x2D = 18.5 kΩ
  • 0x2E = 18.8 kΩ
  • 0x2F = 19.2 kΩ
  • 0x30 = 19.6 kΩ
  • 0x31 = 20 kΩ
  • 0x32 = 20.3 kΩ
  • 0x33 = 20.7 kΩ
  • 0x34 = 21.3 kΩ
  • 0x35 = 21.7 kΩ
  • 0x36 = 22.1 kΩ
  • 0x37 = 22.5 kΩ
  • 0x38 = 22.8 kΩ
  • 0x39 = 23.2 kΩ
  • 0x3A = 23.6 kΩ
  • 0x3B = 24 kΩ
  • 0x3C = 24.6 kΩ
  • 0x3D = 25 kΩ
  • 0x3E = 25.3 kΩ
  • 0x3F = 25.7 kΩ

1.538 R844 (Offset = 0x34C)

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Table 1-540 R844 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:0PLL3_LF_R4R/W0x0 PLL Loop Filter R4 setting
ROM=Y, EEPROM=N
  • 0x0 = 0.0139 kΩ
  • 0x1 = 0.51 kΩ
  • 0x2 = 0.826 kΩ
  • 0x3 = 1.23 kΩ
  • 0x4 = 1.85 kΩ
  • 0x5 = 2.26 kΩ
  • 0x6 = 2.57 kΩ
  • 0x7 = 2.97 kΩ
  • 0x8 = 3.3 kΩ
  • 0x9 = 3.75 kΩ
  • 0xA = 4.07 kΩ
  • 0xB = 4.47 kΩ
  • 0xC = 5.09 kΩ
  • 0xD = 5.5 kΩ
  • 0xE = 5.81 kΩ
  • 0xF = 6.22 kΩ
  • 0x10 = 6.57 kΩ
  • 0x11 = 7.01 kΩ
  • 0x12 = 7.33 kΩ
  • 0x13 = 7.73 kΩ
  • 0x14 = 8.36 kΩ
  • 0x15 = 8.76 kΩ
  • 0x16 = 9.08 kΩ
  • 0x17 = 9.48 kΩ
  • 0x18 = 9.81 kΩ
  • 0x19 = 10.3 kΩ
  • 0x1A = 10.6 kΩ
  • 0x1B = 11 kΩ
  • 0x1C = 11.6 kΩ
  • 0x1D = 12 kΩ
  • 0x1E = 12.3 kΩ
  • 0x1F = 12.7 kΩ
  • 0x20 = 13 kΩ
  • 0x21 = 13.5 kΩ
  • 0x22 = 13.8 kΩ
  • 0x23 = 14.2 kΩ
  • 0x24 = 14.8 kΩ
  • 0x25 = 15.2 kΩ
  • 0x26 = 15.6 kΩ
  • 0x27 = 16 kΩ
  • 0x28 = 16.3 kΩ
  • 0x29 = 16.7 kΩ
  • 0x2A = 17.1 kΩ
  • 0x2B = 17.5 kΩ
  • 0x2C = 18.1 kΩ
  • 0x2D = 18.5 kΩ
  • 0x2E = 18.8 kΩ
  • 0x2F = 19.2 kΩ
  • 0x30 = 19.6 kΩ
  • 0x31 = 20 kΩ
  • 0x32 = 20.3 kΩ
  • 0x33 = 20.7 kΩ
  • 0x34 = 21.3 kΩ
  • 0x35 = 21.7 kΩ
  • 0x36 = 22.1 kΩ
  • 0x37 = 22.5 kΩ
  • 0x38 = 22.8 kΩ
  • 0x39 = 23.2 kΩ
  • 0x3A = 23.6 kΩ
  • 0x3B = 24 kΩ
  • 0x3C = 24.6 kΩ
  • 0x3D = 25 kΩ
  • 0x3E = 25.3 kΩ
  • 0x3F = 25.7 kΩ

1.539 R845 (Offset = 0x34D)

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Table 1-541 R845 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:3PLL3_LF_C3R/W0x0 PLL Loop Filter C3 setting
ROM=Y, EEPROM=N
  • 0x0 = 0 pF
  • 0x1 = 10 pF
  • 0x2 = 20 pF
  • 0x3 = 30 pF
  • 0x4 = 40 pF
  • 0x5 = 50 pF
  • 0x6 = 60 pF
  • 0x7 = 70 pF
2:0PLL3_LF_C4R/W0x0 PLL Loop Filter C4 setting
ROM=Y, EEPROM=N
  • 0x0 = 0 pF
  • 0x1 = 10 pF
  • 0x2 = 20 pF
  • 0x3 = 30 pF
  • 0x4 = 40 pF
  • 0x5 = 50 pF
  • 0x6 = 60 pF
  • 0x7 = 70 pF

1.540 R846 (Offset = 0x34E)

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Table 1-542 R846 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL3_RDIV_8:8R/W0x0 See Register 847

1.541 R847 (Offset = 0x34F)

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Table 1-543 R847 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_RDIVR/W0x1 PLL R Divider
ROM=Y, EEPROM=Y

1.542 R848 (Offset = 0x350)

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Table 1-544 R848 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4PLL3_RDIV_XO_ENR/W0x0 APLL reference source is from XO. Must also enable XO to drive this APLL with XO_OUT_BUF_EN[3] = 1
ROM=Y, EEPROM=Y
3PLL3_RDIV_XO_DBLR_ENR/W0x0 Enables XO Doubler
ROM=Y, EEPROM=Y
2PLL3_RDIV_BYPASS_ENR/W0x0 Bypass R Divider
ROM=Y, EEPROM=Y
1:0PLL3_RDIV_MUX_SELR/W0x0 Select R Divider input: 0=XO, 1=VCO1 feedback divider, 2=VCO2 feedback divider
ROM=Y, EEPROM=Y
  • 0x0 = XO
  • 0x1 = VCO1 feedback divider
  • 0x2 = VCO2 feedback divider

1.543 R849 (Offset = 0x351)

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Table 1-545 R849 Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDR0x0 Reserved
0PLL3_NDIV_8:8R/W0x0 See Register 850

1.544 R850 (Offset = 0x352)

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Table 1-546 R850 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NDIVR/W0x40 PLL N Divider
ROM=Y, EEPROM=Y

1.545 R851 (Offset = 0x353)

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Table 1-547 R851 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NUM_MSBR/W0x4C When PLL3_MODE is set for 24 bit fractional. PLL3_NUM_MSB is effective PLL3_NUM[23:16]. Other PLL3_NUM and PLL3_DEN bits in programmable mode are in PLL3_NUM field. When in 40-bit fixed denominator PLL mode, then PLL3_NUM_MSB is unused.
ROM=Y, EEPROM=Y

1.546 R852 (Offset = 0x354)

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Table 1-548 R852 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NUM_39:32R/W0x4C See Register 856

1.547 R853 (Offset = 0x355)

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Table 1-549 R853 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NUM_31:24R/W0xE7 See Register 856

1.548 R854 (Offset = 0x356)

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Table 1-550 R854 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NUM_23:16R/W0xC5 See Register 856

1.549 R855 (Offset = 0x357)

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Table 1-551 R855 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NUM_15:8R/W0x1 See Register 856

1.550 R856 (Offset = 0x358)

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Table 1-552 R856 Field Descriptions
BitFieldTypeResetDescription
7:0PLL3_NUMR/W0xE When PLL3_MODE = 1 (40-bit fixed denominator) mode then PLL3_NUM contains the APLL3 numerator. When PLL3_MODE = 0 (24-bit programmable denominator) then PLL3_NUM[23:0] stores the programmable PLL3 denominator and PLL3_NUM[39:24] stores the 16 LSBs of the PLL3 numerator. Total PLL3 numerator is calculated with PLL3_NUM_MSB as the 8 MSBs. In 24-bit programmable denominator mode PLL3_NUM[23:0] = 0 is 224.
ROM=Y, EEPROM=Y

1.551 R857 (Offset = 0x359)

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Table 1-553 R857 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:4PLL3_DTHRMODER/W0x0 PLL MASH Dither Mode
ROM=Y, EEPROM=N
  • 0x0 = Constant Dither MACC2
  • 0x1 = Constant Dither MACC2 and MACC3
  • 0x2 = LFSR Dither MACC2
  • 0x3 = Dither Disabled
3:1PLL3_ORDERR/W0x0 PLL MASH Order
ROM=Y, EEPROM=N
  • 0x0 = Integer Mode Divider
  • 0x1 = 1st
  • 0x2 = 2nd
  • 0x3 = 3rd
0PLL3_MODER/W0x0 In APLL 24-bit num/den mode, APLL denominator is programmable. Recommended not for use with DPLL mode. In 24-bit mode, the denominator is stored in PLL3_NUM[23:0] The numerator is stored in (PLL3_NUM_MSB << 16) + PLL3_NUM[39:24].

In APLL 40-bit mode, APLL denominator is fixed. For use with DPLL.
ROM=Y, EEPROM=Y
  • 0x0 = APLL 24-bit num/den
  • 0x1 = APLL 40-bit num (Req for DPLL)

1.552 R858 (Offset = 0x35A)

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Table 1-554 R858 Field Descriptions
BitFieldTypeResetDescription
7:0APLL3_NUM_STAT_39:32R0x0 See Register 862

1.553 R859 (Offset = 0x35B)

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Table 1-555 R859 Field Descriptions
BitFieldTypeResetDescription
7:0APLL3_NUM_STAT_31:24R0x0 See Register 862

1.554 R860 (Offset = 0x35C)

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Table 1-556 R860 Field Descriptions
BitFieldTypeResetDescription
7:0APLL3_NUM_STAT_23:16R0x0 See Register 862

1.555 R861 (Offset = 0x35D)

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Table 1-557 R861 Field Descriptions
BitFieldTypeResetDescription
7:0APLL3_NUM_STAT_15:8R0x0 See Register 862

1.556 R862 (Offset = 0x35E)

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Table 1-558 R862 Field Descriptions
BitFieldTypeResetDescription
7:0APLL3_NUM_STATR0x0 Readback current effective APLL3 Numerator after FDEV and/or DPLL correction
ROM=N, EEPROM=N

1.557 R864 (Offset = 0x360)

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Table 1-559 R864 Field Descriptions
BitFieldTypeResetDescription
7:4PLL3_VCO_BUF_OUT_ENR/W0x0 Enables VCO3 to: [0] -> VCO3 Post-divider, [1] -> VCO3 Auxiliary Buffer (TDC1 Reference Clock Buffer, TDC2 Reference Clock Buffer, APLL1 Reference Clock Buffer, APLL2 Reference Clock Buffer, Window Monitor), [2] -> APLL3 N-Divider, [3] -> DPLL3 N-Divider
ROM=Y, EEPROM=Y
3PLL3_VCO_DIV_SYNC_ENR/W0x1 PLL3 Divider Sync Enable. Enables synchronization of post-dividers and reference dividers for PLL3.
ROM=Y, EEPROM=N
2:0PLL3_PRI_DIVR/W0x1 Sets the VCO3 primary divider divide value from 1 to 8 (div = field value + 1)
ROM=Y, EEPROM=Y
  • 0x0 = 1
  • 0x1 = 2
  • 0x2 = 3
  • 0x3 = 4
  • 0x4 = 5
  • 0x5 = 6
  • 0x6 = 7
  • 0x7 = 8

1.558 R865 (Offset = 0x361)

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Table 1-560 R865 Field Descriptions
BitFieldTypeResetDescription
7:6PLL3_VCO_DIV_SELR/W0x0 Selects APLL3 P1 post-divider block or APLL3 P1 followed by additional divide-by 2 block.
ROM=Y, EEPROM=Y
  • 0x0 = PLL3 drive off
  • 0x1 = Reserved
  • 0x2 = Divide-by-1-to-8 direct
  • 0x3 = Divide-by-1-to-8 and /2
5PLL3_VCO_CHAN_DRVR_IN_ENR/W0x1 Enables the selected clock (div1to8 or div2) to the VCO3 to Outputs Output Buffer. See PLL3_VCO_DIV1TO8_EN and PLL3_VCO_DIV2_EN. Optimization to prevent unused domain from interacting with active domains. Always on if using PLL3. Might be on to help reduce crosstalk from APLL3.
ROM=Y, EEPROM=Y
4PLL3_P1_OUT14_15_ENR/W0x0 Enable VCO3 P1 divider output driver to channel output bank OUT14_15
ROM=Y, EEPROM=Y
3PLL3_P1_OUT8_13_ENR/W0x0 Enable VCO3 P1 divider output driver to channel output bank OUT8_13
ROM=Y, EEPROM=Y
2PLL3_P1_OUT4_7_ENR/W0x0 Enable VCO3 P1 divider output driver to channel output bank OUT4_7
ROM=Y, EEPROM=Y
1PLL3_P1_OUT2_3_ENR/W0x0 Enable VCO3 P1 divider output driver to channel output bank OUT2_3
ROM=Y, EEPROM=Y
0PLL3_P1_OUT0_1_ENR/W0x0 Enable VCO3 P1 divider output driver to channel output bank OUT0_1
ROM=Y, EEPROM=Y

1.559 R866 (Offset = 0x362)

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Table 1-561 R866 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:3PLL3_VCO_BUF_2REF_ENR/W0x0 Enables the APLL3 Div-by-2 cascade divider to [0] -> APLL1 and [1] -> APLL2 reference input for cascade mode.
ROM=Y, EEPROM=Y
2PLL3_WIN_DET_DRVR_ENR/W0x0 Enables the APLL3 Div-by-2 cascade divider to reference window detectors input buffer,
ROM=Y, EEPROM=N
1:0PLL3_VCO_BUF_FB_TDC_ENR/W0x0 Enables APLL3 Div-by-4 cascade divider to TDC1 and TDC2 for cascade mode [0] = TDC1 driver enable [1] = TDC2 driver enable.
ROM=Y, EEPROM=N

1.560 R872 (Offset = 0x368)

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Table 1-562 R872 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5:4RESERVEDR0x0 Reserved
3PLL3_RDIV_OUTPUT_ENR/W0x0 If GPIOx_SEL selects PLL3 R/2 as an output. Then this bit must be set along with STATUS_MUX_DIV2_EN=1.
ROM=N, EEPROM=N
2:0RESERVEDR0x0 Reserved

1.561 R882 (Offset = 0x372)

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Table 1-563 R882 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5PLL3_NDIV_OUTPUT_ENR/W0x0 If GPIOx_SEL selects PLL3 N/2 as an output. Then this bit must be set along with STATUS_MUX_DIV2_EN=1.
ROM=N, EEPROM=N
4:0RESERVEDR0x0 Reserved

1.562 R961 (Offset = 0x3C1)

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Table 1-564 R961 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_0_ENR/W0x1 OUT0 Enable. If CMOS on OUT0 is used, this enable must also be set.
ROM=Y, EEPROM=Y
5:0OUT_0_FMTR/W0x0 Remix of OUT_0_VOD and OUT_0_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.563 R962 (Offset = 0x3C2)

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Table 1-565 R962 Field Descriptions
BitFieldTypeResetDescription
7OUT_0_CAP_ENR/W0x1 If enable, this output capacitor reduces the slew rate of the output clock.
ROM=Y, EEPROM=N
6OUT_0_STATIC_LOWR/W0x0 When OUT0 is forced to a static output, this bit determines if the output voltage will be
0: Static Low
1: Static High
ROM=Y, EEPROM=N
  • 0x0 = L
  • 0x1 = H
5OUT_0_P_CMOS_ENR/W0x0 OUT0P CMOS Enable. Overrides the OUT_0_VOD setting and makes OUT_0 CMOS. Setting this bit enables of the positive terminal of OUT0 for CMOS outputs. OUT_0_ENABLE must also be set.
ROM=Y, EEPROM=Y
4OUT_0_N_CMOS_ENR/W0x0 OUT0N CMOS Enable. Setting this bit enables of the negative terminal of OUT0 for CMOS outputs. OUT_0_ENABLE must also be set.
ROM=Y, EEPROM=Y
3OUT_0_P_INVERT_POLARITYR/W0x0 OUT0P CMOS Invert Polarity. Setting this bit inverts the polarity of the positive terminal of OUT0 for CMOS outputs.
ROM=Y, EEPROM=N
2OUT_0_N_INVERT_POLARITYR/W0x0 OUT0N CMOS Invert Polarity. Setting this bit inverts the polarity of the negative terminal of OUT0 for CMOS outputs.
ROM=Y, EEPROM=N
1OUT_0_P_FORCELOWR/W0x0 OUT0P CMOS Force Low. Setting this bit forces the positive terminal of OUT0 low.
ROM=Y, EEPROM=N
0OUT_0_N_FORCELOWR/W0x0 OUT0N CMOS Force Low. Setting this bit forces the negative terminal of OUT0 low.
ROM=Y, EEPROM=N

1.564 R963 (Offset = 0x3C3)

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Table 1-566 R963 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_CONFIGURATIONR/W0x0 OUT0 configuration. Selects from CH0 Bypass, CH1 Bypass, CHDIV0, CHDIV1, CH0/2 low-noise divide by two path, SYSREF, SYSREF + Analog Delay, or static DC H/L.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH0/2
  • 0x14 = CHDIV1
  • 0x20 = SYSREF+ADLY
  • 0x21 = SYSREF
  • 0x22 = Static DC
  • 0x28 = CHDIV0
  • 0x40 = CH1 Bypass
  • 0x80 = CH0 Bypass

1.565 R964 (Offset = 0x3C4)

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Table 1-567 R964 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_1_ENR/W0x1 OUT1 Enable. If CMOS on OUT1 is used, this enable must also be set.
ROM=Y, EEPROM=Y
5:0OUT_1_FMTR/W0x0 Remix of OUT_1_VOD and OUT_1_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.566 R965 (Offset = 0x3C5)

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Table 1-568 R965 Field Descriptions
BitFieldTypeResetDescription
7OUT_1_CAP_ENR/W0x1 ROM=Y, EEPROM=N
6OUT_1_STATIC_LOWR/W0x0 When OUT1 is forced to a static output, this bit determines if the output voltage will be 0=Static Low or 1=Static High
ROM=Y, EEPROM=N
  • 0x0 = L
  • 0x1 = H
5OUT_1_P_CMOS_ENR/W0x0 OUT1P CMOS Enable. Setting this bit enables the positive terminal of OUT1 for CMOS outputs.
ROM=Y, EEPROM=Y
4OUT_1_N_CMOS_ENR/W0x0 OUT1N CMOS Enable. Setting this bit enables the negative terminal of OUT1 for CMOS outputs.
ROM=Y, EEPROM=Y
3OUT_1_P_INVERT_POLARITYR/W0x0 OUT1P CMOS Invert Polarity. Setting this bit inverts the polarity of the positive terminal of OUT1 for CMOS outputs.
ROM=Y, EEPROM=N
2OUT_1_N_INVERT_POLARITYR/W0x0 OUT1N CMOS Invert Polarity. Setting this bit inverts the polarity of the negative terminal of OUT1 for CMOS outputs.
ROM=Y, EEPROM=N
1OUT_1_P_FORCELOWR/W0x0 OUT1P CMOS Force Low. Setting this bit forces the positive terminal of OUT1 low.
ROM=Y, EEPROM=N
0OUT_1_N_FORCELOWR/W0x0 OUT1N CMOS Force Low. Setting this bit forces the negative terminal of OUT1 low.
ROM=Y, EEPROM=N

1.567 R966 (Offset = 0x3C6)

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Table 1-569 R966 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_1_CONFIGURATIONR/W0x0 OUT1 configuration. Selects from CH0 Bypass, CH1 Bypass, CHDIV0, CHDIV1, CH0/2 low-noise divide by two path, SYSREF, SYSREF + Analog Delay, or static DC H/L.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH0/2
  • 0x14 = CHDIV1
  • 0x20 = SYSREF+ADLY
  • 0x21 = SYSREF
  • 0x22 = Static DC
  • 0x28 = CHDIV0
  • 0x40 = CH1 Bypass
  • 0x80 = CH0 Bypass

1.568 R967 (Offset = 0x3C7)

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Table 1-570 R967 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1OUT_0_1_CMOS_OUT_VOLTAGE_SELR/W0x0 CMOS LDO Voltage. Selects CMOS LDO voltage.
ROM=Y, EEPROM=Y
  • 0x0 = 1.8 V
  • 0x1 = 2.65 V
0OUT_0_1_CMOS_OUT_LDO_ENR/W0x0 CMOS LDO Enable. Enables LDO used for CMOS outputs. Must be enabled for CMOS mode.
ROM=Y, EEPROM=Y

1.569 R968 (Offset = 0x3C8)

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Table 1-571 R968 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:1OUT_0_1_ZDM_TDC_SELR/W0x0 Select zero delay output to TDC's
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = TDC1
  • 0x2 = TDC2
  • 0x4 = TDC3
0OUT_0_1_ZDM_ENR/W0x0 Enable the output from CH_DIV0_1 to be used as DPLL feedback input for zero delay mode
ROM=Y, EEPROM=N

1.570 R969 (Offset = 0x3C9)

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Table 1-572 R969 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_0_1_DIV_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
5OUT_0_1_DIV_SYNC_ENR/W0x0 OUT0_1 Divider Sync Enable. Enables synchronization of chandiv and div2 dividers for OUT0_1.
ROM=Y, EEPROM=N
4OUT_0_1_SR_DIV_SYNC_ENR/W0x0 OUT0_1 SYSREF Divider Sync Enable. Enables synchronization of SYSREF dividers for OUT0_1.
ROM=Y, EEPROM=N
3OUT_0_1_CH0_CHAN_POL_SELR/W0x0 OUT0_1 Ch0 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the Ch0 channel divider.
ROM=Y, EEPROM=N
2OUT_0_1_CH1_CHAN_POL_SELR/W0x0 OUT0_1 Ch1 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the Ch1 channel divider.
ROM=Y, EEPROM=N
1OUT_0_1_CH0_DIV_ENR/W0x0 OUT0_1 Ch0 ChanDiv Enable. Enables the Ch0 channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y
0OUT_0_1_CH1_DIV_ENR/W0x0 OUT0_1 Ch1 ChanDiv Enable. Enables the Ch1 channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y

1.571 R972 (Offset = 0x3CC)

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Table 1-573 R972 Field Descriptions
BitFieldTypeResetDescription
7:2RESERVEDR0x0 Reserved
1OUT_0_1_CH0_CH_DIV_SR_MUX_CLK_SELR/W0x0 OUT0_1 Ch0 ChanDiv to SYSREF Input Clock Select. When set, the Ch0 channel divider output is inverted before being fed to the SYSREF.
ROM=Y, EEPROM=N
  • 0x0 = POS POL to SR_DIV
  • 0x1 = NEG POL to SR_DIV
0RESERVEDR0x0 Reserved

1.572 R973 (Offset = 0x3CD)

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Table 1-574 R973 Field Descriptions
BitFieldTypeResetDescription
7:2OUT_0_1_CLK_IN_FANOUTR/W0x0 OUT0_1 input clock fanout. Distributes the input clock to the channel dividers and the standalone divide-by-2s.
ROM=Y, EEPROM=Y
  • 0x0 = DISABLED
  • 0x3 = IN1 to CHDIV1
  • 0x4 = IN0 to SYSREF
  • 0x7 = IN0 to SYSREF, IN1 to CHDIV1
  • 0xC = IN0 to CHDIV0
  • 0xF = IN0 to CHDIV0, IN1 to CHDIV1
  • 0x10 = IN0 to CH0/2 (OUT0)
  • 0x13 = IN0 to CH0/2 (OUT0), IN1 to CHDIV1 (OUT1)
  • 0x14 = IN0 to CH0/2 (OUT0) and SYSREF (OUT1)
  • 0x1C = IN0 to CH0/2 (OUT0) and CHDIV0 (OUT1)
  • 0x20 = IN0 to CH0/2 (OUT1)
  • 0x23 = IN0 to CH0/2 (OUT1), IN1 to CHDIV1 (OUT0)
  • 0x24 = IN0 to CH0/2 (OUT1) and SYSREF (OUT0)
  • 0x2C = IN0 to CH0/2 (OUT1) and CHDIV0 (OUT0)
  • 0x30 = IN0 to CH0/2 (OUT0 and OUT1)
1:0RESERVEDR0x0 Reserved

1.573 R974 (Offset = 0x3CE)

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Table 1-575 R974 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_0_1_CH0_CH_STATIC_OFFSET_11:8R/W0x0 See Register 975

1.574 R975 (Offset = 0x3CF)

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Table 1-576 R975 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_CH0_CH_STATIC_OFFSETR/W0x0 CH0_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.575 R976 (Offset = 0x3D0)

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Table 1-577 R976 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_0_1_CH1_CH_STATIC_OFFSET_11:8R/W0x0 See Register 977

1.576 R977 (Offset = 0x3D1)

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Table 1-578 R977 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_CH1_CH_STATIC_OFFSETR/W0x0 CH1_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.577 R978 (Offset = 0x3D2)

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Table 1-579 R978 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_0_1_CH0_CH_DIV_11:8R/W0x0 See Register 979

1.578 R979 (Offset = 0x3D3)

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Table 1-580 R979 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_CH0_CH_DIVR/W0x0 OUT0_1 Ch0 Channel Divider (ChanDiv) Divide Value.
ROM=Y, EEPROM=Y

1.579 R980 (Offset = 0x3D4)

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Table 1-581 R980 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_0_1_CH1_CH_DIV_11:8R/W0x0 See Register 981

1.580 R981 (Offset = 0x3D5)

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Table 1-582 R981 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_CH1_CH_DIVR/W0x0 OUT0_1 Ch1 Channel Divider (ChanDiv) Divide Value.
ROM=Y, EEPROM=Y

1.581 R982 (Offset = 0x3D6)

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Table 1-583 R982 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_0_1_SR_ANA_DELAYR/W0x0 OUT0_1 SYSREF Analog Delay. Specified here in multiples of one delay step duration.
ROM=Y, EEPROM=N

1.582 R983 (Offset = 0x3D7)

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Table 1-584 R983 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_0_1_SR_ANA_DELAY_DIV2_SELR/W0x0 OUT0_1 SYSREF Analog Delay Div By 2 Select. Divides the incoming clock by 2 to double the delay step size. Useful for increasing analog delay range, given high incoming clock frequencies.
ROM=Y, EEPROM=N
4OUT_0_1_SR_ANA_DELAY_ENR/W0x0 OUT0_1 SYSREF Analog Delay Enable.
ROM=Y, EEPROM=N
3OUT_0_1_SR_ANA_DELAY_SMALL_STEP_ENR/W0x0 OUT0_1 SYSREF Analog Delay Small Step Enable. If set to 1, the analog delay generator will use both rising and falling edges of the incoming clock to halve delay step size. Useful for when large pre-divider values have been used.
ROM=Y, EEPROM=N
2:0OUT_0_1_SR_ANA_DELAY_RANGER/W0x0 Analog delay range is set according to the period entering the SYSREF analog delay block. The period can be calculated as (OUT_x_y_SR_ANA_DELAY_DIV2_SEL + 1) / (OUT_x_y_SR_ANA_DELAY_SMALL_STEP_EN + 1) / VCO post divider frequency. Calculated range must fall between 333 ps and 1050 ps.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = 333 ps to 450 ps
  • 0x3 = > 450 ps to 600 ps
  • 0x4 = > 600 ps to 750 ps
  • 0x5 = > 750 ps to 1050 ps
  • 0x6 = Reserved
  • 0x7 = Reserved

1.583 R984 (Offset = 0x3D8)

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Table 1-585 R984 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_0_1_SR_DDLYR/W0x0 OUT0_1 SYSREF Digital Delay Value. Measured in VCO half-cycles.
ROM=Y, EEPROM=N

1.584 R985 (Offset = 0x3D9)

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Table 1-586 R985 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_0_1_SR_DIV_19:16R/W0x0 See Register 987

1.585 R986 (Offset = 0x3DA)

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Table 1-587 R986 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_SR_DIV_15:8R/W0x0 See Register 987

1.586 R987 (Offset = 0x3DB)

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Table 1-588 R987 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_SR_DIVR/W0x0 OUT0_1 SYSREF Divide Value.
ROM=Y, EEPROM=N

1.587 R988 (Offset = 0x3DC)

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Table 1-589 R988 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0OUT_0_1_SR_DIV_STATIC_OFFSET_14:8R/W0x0 See Register 989

1.588 R989 (Offset = 0x3DD)

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Table 1-590 R989 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_0_1_SR_DIV_STATIC_OFFSETR/W0x0 OUT_0_1_SR_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization
ROM=Y, EEPROM=N

1.589 R990 (Offset = 0x3DE)

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Table 1-591 R990 Field Descriptions
BitFieldTypeResetDescription
7OUT_0_1_SR_REQ_MODER/W0x0 OUT0_1 SYSREF Mute Enable
ROM=Y, EEPROM=N
6OUT_0_1_SR_GPIO_ENR/W0x0 Enable SYSREF to digital for SYSREF request resampling, continuous SYSREF, 1-PPS GPIO output, 1-PPS phase validation. Only one OUT_x_y_SR_GPIO_EN should be enabled at a time.
ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:2OUT_0_1_PULSE_COUNTR/W0x0 OUT0_1 SYSREF Pulse Count. The number of SYSREF pulses which will be generated by a SYSREF request.
ROM=Y, EEPROM=N
1:0OUT_0_1_SR_MODER/W0x0 OUT0_1 SYSREF Mode. Selects Pulser mode, Continuous mode, or None.
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = Continuous
  • 0x2 = Pulser

1.590 R991 (Offset = 0x3DF)

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Table 1-592 R991 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_0_1_SR_CH0_DIV_BYPASSR/W0x0 OUT0_1 cascaded SYSREF bypass mux. If set, bypasses CHDIV0 for the SYSREF input clock. This is useful for minimizing the step size of the digital delay adjustments on the SYSREF clock.
ROM=Y, EEPROM=N
  • 0x0 = ChanDiv input to SysRef
  • 0x1 = Bypass ChanDiv
4:0RESERVEDR0x0 Reserved

1.591 R1024 (Offset = 0x400)

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Table 1-593 R1024 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_2_ENR/W0x1 OUT2 Enable.
ROM=Y, EEPROM=Y
5:0OUT_2_FMTR/W0x0 Remix of OUT_2_VOD and OUT_2_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.592 R1025 (Offset = 0x401)

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Table 1-594 R1025 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3OUT_2_CAP_ENR/W0x1 ROM=Y, EEPROM=N
2:0OUT_2_CONFIGURATIONR/W0x0 OUT2 configuration.
ROM=Y, EEPROM=Y and N
  • 0x2 = Static DC
  • 0x3 = CHDIV
  • 0x4 = BYPASS
  • 0x5 = BYPASS

1.593 R1026 (Offset = 0x402)

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Table 1-595 R1026 Field Descriptions
BitFieldTypeResetDescription
7OUT_2_CHAN_POL_SELR/W0x0 OUT2 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
6:5OUT_2_CLK_MUXR/W0x0 OUT2 Input Clock Select. Selects the input clock which will be used to drive the output.
ROM=Y, EEPROM=Y
  • 0x0 = PLL3
  • 0x1 = PLL2
  • 0x2 = PLL1_PRI
4RESERVEDR0x0 Reserved
3OUT_2_DIV_ENR/W0x0 OUT2 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y
2:0OUT_2_CH_MUX_SELR/W0x0 OUT2 Clock Enable. Bit 2, if set, passes the selected VCO1 clock (VCO1P or VCO1S), to the second stage of clock selection. Bit 1 and Bit0 enable the selected clock to drive the channel divider and the channel divider retimer respectively.
ROM=Y, EEPROM=Y
  • 0x0 = PLL2->BYPASS
  • 0x3 = PLL2->CHDIV
  • 0x4 = PLL1->BYPASS
  • 0x7 = PLL1->CHDIV

1.594 R1027 (Offset = 0x403)

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Table 1-596 R1027 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4OUT_2_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
3OUT_2_SYNC_ENR/W0x0 OUT2 ChanDiv Sync Enable. Enables synchronization of chandiv dividers for OUT2.
ROM=Y, EEPROM=N
2:0RESERVEDR0x0 Reserved

1.595 R1028 (Offset = 0x404)

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Table 1-597 R1028 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_2_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1029

1.596 R1029 (Offset = 0x405)

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Table 1-598 R1029 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_2_CH_STATIC_OFFSETR/W0x0 OUT_2_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.597 R1030 (Offset = 0x406)

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Table 1-599 R1030 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_2_CH_DIV_11:8R/W0x0 See Register 1031

1.598 R1031 (Offset = 0x407)

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Table 1-600 R1031 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_2_CH_DIVR/W0x0 OUT2 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.599 R1056 (Offset = 0x420)

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Table 1-601 R1056 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_3_ENR/W0x1 OUT3 Enable.
ROM=Y, EEPROM=Y
5:0OUT_3_FMTR/W0x0 Remix of OUT_3_VOD and OUT_3_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.600 R1057 (Offset = 0x421)

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Table 1-602 R1057 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3OUT_3_CAP_ENR/W0x1 ROM=Y, EEPROM=N
2:0OUT_3_CONFIGURATIONR/W0x0 OUT3 configuration.
ROM=Y, EEPROM=Y and N
  • 0x2 = Static DC
  • 0x3 = CHDIV
  • 0x4 = BYPASS
  • 0x5 = BYPASS

1.601 R1058 (Offset = 0x422)

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Table 1-603 R1058 Field Descriptions
BitFieldTypeResetDescription
7OUT_3_CHAN_POL_SELR/W0x0 OUT3 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
6:5OUT_3_CLK_MUXR/W0x0 OUT3 Input Clock Select. Selects the input clock which will be used to drive the output.
ROM=Y, EEPROM=Y
  • 0x0 = PLL3
  • 0x1 = PLL2
  • 0x2 = PLL1_PRI
4RESERVEDR0x0 Reserved
3OUT_3_DIV_ENR/W0x0 OUT3 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y
2:0OUT_3_CH_MUX_SELR/W0x0 OUT3 Clock Enable. Bit 2, if set, passes the selected VCO1 clock (VCO1P or VCO1S), to the second stage of clock selection. Bit 1 and Bit0 enable the selected clock to drive the channel divider and the channel divider retimer respectively.
ROM=Y, EEPROM=Y
  • 0x0 = PLL2->BYPASS
  • 0x3 = PLL2->CHDIV
  • 0x4 = PLL1->BYPASS
  • 0x7 = PLL1->CHDIV

1.602 R1059 (Offset = 0x423)

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Table 1-604 R1059 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4OUT_3_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
3OUT_3_SYNC_ENR/W0x0 OUT3 ChanDiv Sync Enable. Enables synchronization of chandiv dividers for OUT3.
ROM=Y, EEPROM=N
2:0RESERVEDR0x0 Reserved

1.603 R1060 (Offset = 0x424)

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Table 1-605 R1060 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_3_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1061

1.604 R1061 (Offset = 0x425)

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Table 1-606 R1061 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_3_CH_STATIC_OFFSETR/W0x0 OUT_3_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.605 R1062 (Offset = 0x426)

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Table 1-607 R1062 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_3_CH_DIV_11:8R/W0x0 See Register 1063

1.606 R1063 (Offset = 0x427)

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Table 1-608 R1063 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_3_CH_DIVR/W0x0 OUT3 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.607 R1088 (Offset = 0x440)

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Table 1-609 R1088 Field Descriptions
BitFieldTypeResetDescription
7:3RESERVEDR0x0 Reserved
2:0OUT_4_5_SR_ANA_DLY_BIASTRIMR/W0x0 Channel Analog Delay Bias Trim
ROM=N, EEPROM=Y

1.608 R1089 (Offset = 0x441)

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Table 1-610 R1089 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_4_ENR/W0x1 OUT4 Enable.
ROM=Y, EEPROM=Y
5:0OUT_4_FMTR/W0x0 Remix of OUT_4_VOD and OUT_4_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.609 R1090 (Offset = 0x442)

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Table 1-611 R1090 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_4_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_4_CONFIGURATIONR/W0x0 OUT4 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.610 R1091 (Offset = 0x443)

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Table 1-612 R1091 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_5_ENR/W0x1 OUT5 Enable.
ROM=Y, EEPROM=Y
5:0OUT_5_FMTR/W0x0 Remix of OUT_5_VOD and OUT_5_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.611 R1092 (Offset = 0x444)

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Table 1-613 R1092 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_5_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_5_CONFIGURATIONR/W0x0 OUT5 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.612 R1093 (Offset = 0x445)

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Table 1-614 R1093 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_4_5_DIV_SYNC_ENR/W0x0 OUT4_5 Divider Sync Enable. Enables synchronization of chandiv dividers for OUT4_5.
ROM=Y, EEPROM=N
4OUT_4_5_SR_DIV_SYNC_ENR/W0x0 OUT4_5 SYSREF Divider Sync Enable. Enables synchronization of SYSREF dividers for OUT4_5.
ROM=Y, EEPROM=N
3:2RESERVEDR0x0 Reserved
1OUT_4_5_CHAN_POL_SELR/W0x0 OUT4_5 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
0OUT_4_5_DIV_ENR/W0x0 OUT4_5 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y

1.613 R1094 (Offset = 0x446)

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Table 1-615 R1094 Field Descriptions
BitFieldTypeResetDescription
7OUT_4_5_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
6OUT_4_5_ZDM_ENR/W0x0 OUT4_5 zero delay output enable
ROM=Y, EEPROM=N
5OUT_4_5_CLK_IN_SELR/W0x0 OUT4_5 Input Clock Select. Selects the input clock which will be used to drive the output: 0 = VCO2, 1 = VCO3
ROM=Y, EEPROM=Y
  • 0x0 = PLL2
  • 0x1 = PLL3
4OUT_4_5_CH_DIV_SR_MUX_CLK_SELR/W0x0 OUT4_5 ChanDiv to SYSREF Clock Select. When set, the channel divider output is inverted before being fed to the SYSREF.
ROM=Y, EEPROM=N
3:0OUT_4_5_CH_MUX_SELR/W0x0 OUT4_5 Input Clock Enable. Enables the selected clock to various inputs: [0] -> ChanDiv, [1] -> ChanDiv Retimer, [2] -> Div2 to OUT4, [3] -> Div2 to OUT5
ROM=Y, EEPROM=Y
  • 0x0 = OFF
  • 0x1 = SYSREF
  • 0x3 = CHDIV
  • 0x4 = DIV2->OUT4
  • 0x5 = DIV2->OUT4, SYSREF->OUT5
  • 0x7 = DIV2->OUT4, CHDIV->OUT5
  • 0x8 = DIV2->OUT5
  • 0x9 = SYSREF->OUT4, DIV2->OUT5
  • 0xB = CHDIV->OUT4, DIV2->OUT5
  • 0xC = DIV2->OUT4, DIV2->OUT5

1.614 R1095 (Offset = 0x447)

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Table 1-616 R1095 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_4_5_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1096

1.615 R1096 (Offset = 0x448)

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Table 1-617 R1096 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_4_5_CH_STATIC_OFFSETR/W0x0 OUT_4_5_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.616 R1097 (Offset = 0x449)

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Table 1-618 R1097 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_4_5_CH_DIV_11:8R/W0x0 See Register 1098

1.617 R1098 (Offset = 0x44A)

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Table 1-619 R1098 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_4_5_CH_DIVR/W0x0 OUT4_5 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.618 R1099 (Offset = 0x44B)

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Table 1-620 R1099 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_4_5_SR_ANA_DELAYR/W0x0 OUT4_5 SYSREF Analog Delay. Specified here in multiples of one delay step duration.
ROM=Y, EEPROM=N

1.619 R1100 (Offset = 0x44C)

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Table 1-621 R1100 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_4_5_SR_ANA_DELAY_DIV2_SELR/W0x0 OUT4_5 SYSREF Analog Delay Div By 2 Select. Divides the incoming clock by 2 to double the delay step size. Useful for increasing analog delay range, given high incoming clock frequencies.
ROM=Y, EEPROM=N
4OUT_4_5_SR_ANA_DELAY_ENR/W0x0 OUT4_5 SYSREF Analog Delay Enable. Enables the analog delay generator. Set to a 0 to save power if analog delay generator is not needed.
ROM=Y, EEPROM=N
3OUT_4_5_SR_ANA_DELAY_SMALL_STEP_ENR/W0x0 OUT4_5 SYSREF Analog Delay Small Step Enable. If set to 1, the analog delay generator will use both rising and falling edges of the incoming clock to halve delay step size. Useful for when large pre-divider values have been used.
ROM=Y, EEPROM=N
2:0OUT_4_5_SR_ANA_DELAY_RANGER/W0x0 Analog delay range is set according to the period entering the SYSREF analog delay block. The period can be calculated as (OUT_x_y_SR_ANA_DELAY_DIV2_SEL + 1) / (OUT_x_y_SR_ANA_DELAY_SMALL_STEP_EN + 1) / VCO post divider frequency. Calculated range must fall between 333 ps and 1050 ps.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = 333 ps to 450 ps
  • 0x3 = > 450 ps to 600 ps
  • 0x4 = > 600 ps to 750 ps
  • 0x5 = > 750 ps to 1050 ps
  • 0x6 = Reserved
  • 0x7 = Reserved

1.620 R1101 (Offset = 0x44D)

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Table 1-622 R1101 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_4_5_SR_DDLYR/W0x0 OUT4_5 SYSREF Digital Delay Value. Measured in VCO half-cycles.
ROM=Y, EEPROM=N

1.621 R1102 (Offset = 0x44E)

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Table 1-623 R1102 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_4_5_SR_DIV_19:16R/W0x0 See Register 1104

1.622 R1103 (Offset = 0x44F)

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Table 1-624 R1103 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_4_5_SR_DIV_15:8R/W0x0 See Register 1104

1.623 R1104 (Offset = 0x450)

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Table 1-625 R1104 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_4_5_SR_DIVR/W0x0 OUT4_5 SYSREF Divide Value.
ROM=Y, EEPROM=N

1.624 R1105 (Offset = 0x451)

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Table 1-626 R1105 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0OUT_4_5_SR_DIV_STATIC_OFFSET_14:8R/W0x0 See Register 1106

1.625 R1106 (Offset = 0x452)

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Table 1-627 R1106 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_4_5_SR_DIV_STATIC_OFFSETR/W0x0 OUT_4_5_SR_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization
ROM=Y, EEPROM=N

1.626 R1107 (Offset = 0x453)

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Table 1-628 R1107 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_4_5_SR_REQ_MODER/W0x0 OUT4_5 SYSREF Mute Enable
ROM=Y, EEPROM=N
5:3OUT_4_5_PULSE_COUNTR/W0x0 OUT4_5 SYSREF Pulse Count. The number of SYSREF pulses which will be generated by a SYSREF request.
ROM=Y, EEPROM=N
2OUT_4_5_SR_GPIO_ENR/W0x0 Enables SYSREF to digital for SYSREF request resampling, continuous SYSREF, or 1-PPS GPIO output. Only one OUT_x_y_SR_GPIO_EN should be enabled at a time.
ROM=Y, EEPROM=N
1:0OUT_4_5_SR_MODER/W0x0 OUT4_5 SYSREF Mode. When these bits are set, the SYSREF operates in Continuous Mode. When cleared, the SYSREF operates in Pulse Mode.
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = Continuous
  • 0x2 = Pulser

1.627 R1108 (Offset = 0x454)

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Table 1-629 R1108 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:5RESERVEDR0x0 Reserved
4OUT_4_5_SR_CH_DIV_BYPASSR/W0x0 OUT4_5 cascaded SYSREF bypass mux. If set, bypasses OUT4_5 channel divider for the SYSREF input clock. This is useful for minimizing the step size of the digital delay adjustments on the SYSREF clock.
ROM=Y, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.628 R1121 (Offset = 0x461)

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Table 1-630 R1121 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_6_ENR/W0x1 OUT6 Enable.
ROM=Y, EEPROM=Y
5:0OUT_6_FMTR/W0x0 Remix of OUT_6_VOD and OUT_6_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.629 R1122 (Offset = 0x462)

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Table 1-631 R1122 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_6_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_6_CONFIGURATIONR/W0x0 OUT6 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.630 R1123 (Offset = 0x463)

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Table 1-632 R1123 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_7_ENR/W0x1 OUT7 Enable.
ROM=Y, EEPROM=Y
5:0OUT_7_FMTR/W0x0 Remix of OUT_7_VOD and OUT_7_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.631 R1124 (Offset = 0x464)

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Table 1-633 R1124 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_7_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_7_CONFIGURATIONR/W0x0 OUT7 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.632 R1125 (Offset = 0x465)

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Table 1-634 R1125 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_6_7_DIV_SYNC_ENR/W0x0 OUT6_7 Divider Sync Enable. Enables synchronization of chandiv dividers for OUT6_7.
ROM=Y, EEPROM=N
4OUT_6_7_SR_DIV_SYNC_ENR/W0x0 OUT6_7 SYSREF Divider Sync Enable. Enables synchronization of SYSREF dividers for OUT6_7.
ROM=Y, EEPROM=N
3:2RESERVEDR0x0 Reserved
1OUT_6_7_CHAN_POL_SELR/W0x0 OUT6_7 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
0OUT_6_7_DIV_ENR/W0x0 OUT6_7 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y

1.633 R1126 (Offset = 0x466)

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Table 1-635 R1126 Field Descriptions
BitFieldTypeResetDescription
7OUT_6_7_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
6RESERVEDR0x0 Reserved
5OUT_6_7_CLK_IN_SELR/W0x0 OUT6_7 Input Clock Select. Selects the input clock which will be used to drive the output: 0 = VCO2, 1 = VCO3
ROM=Y, EEPROM=Y
  • 0x0 = PLL2
  • 0x1 = PLL3
4OUT_6_7_CH_DIV_SR_MUX_CLK_SELR/W0x0 OUT6_7 ChanDiv to SYSREF Clock Select. When set, the channel divider output is inverted before being fed to the SYSREF.
ROM=Y, EEPROM=N
3:0OUT_6_7_CH_MUX_SELR/W0x0 OUT6_7 Input Clock Enable. Enables the selected clock to various inputs: [0] -> ChanDiv, [1] -> ChanDiv Retimer, [2] -> Div2 to OUT6, [3] -> Div2 to OUT7
ROM=Y, EEPROM=Y
  • 0x0 = OFF
  • 0x1 = SYSREF
  • 0x3 = CHDIV
  • 0x4 = DIV2->OUT6
  • 0x5 = DIV2->OUT6, SYSREF->OUT7
  • 0x7 = DIV2->OUT6, CHDIV->OUT7
  • 0x8 = DIV2->OUT7
  • 0x9 = SYSREF->OUT6, DIV2->OUT7
  • 0xB = CHDIV->OUT6, DIV2->OUT7
  • 0xC = DIV2->OUT6, DIV2->OUT7

1.634 R1127 (Offset = 0x467)

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Table 1-636 R1127 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_6_7_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1128

1.635 R1128 (Offset = 0x468)

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Table 1-637 R1128 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_6_7_CH_STATIC_OFFSETR/W0x0 OUT_6_7_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.636 R1129 (Offset = 0x469)

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Table 1-638 R1129 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_6_7_CH_DIV_11:8R/W0x0 See Register 1130

1.637 R1130 (Offset = 0x46A)

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Table 1-639 R1130 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_6_7_CH_DIVR/W0x0 OUT6_7 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.638 R1131 (Offset = 0x46B)

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Table 1-640 R1131 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_6_7_SR_ANA_DELAYR/W0x0 OUT6_7 SYSREF Analog Delay. Specified here in multiples of one delay step duration.
ROM=Y, EEPROM=N

1.639 R1132 (Offset = 0x46C)

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Table 1-641 R1132 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_6_7_SR_ANA_DELAY_DIV2_SELR/W0x0 OUT6_7 SYSREF Analog Delay Div By 2 Select. Divides the incoming clock by 2 to double the delay step size. Useful for increasing analog delay range, given high incoming clock frequencies.
ROM=Y, EEPROM=N
4OUT_6_7_SR_ANA_DELAY_ENR/W0x0 OUT6_7 SYSREF Analog Delay Enable. Enables the analog delay generator. Set to a 0 to save power if analog delay generator is not needed.
ROM=Y, EEPROM=N
3OUT_6_7_SR_ANA_DELAY_SMALL_STEP_ENR/W0x0 OUT6_7 SYSREF Analog Delay Small Step Enable. If set to 1, the analog delay generator will use both rising and falling edges of the incoming clock to halve delay step size. Useful for when large pre-divider values have been used.
ROM=Y, EEPROM=N
2:0OUT_6_7_SR_ANA_DELAY_RANGER/W0x0 Analog delay range is set according to the period entering the SYSREF analog delay block. The period can be calculated as (OUT_x_y_SR_ANA_DELAY_DIV2_SEL + 1) / (OUT_x_y_SR_ANA_DELAY_SMALL_STEP_EN + 1) / VCO post divider frequency. Calculated range must fall between 333 ps and 1050 ps.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = 333 ps to 450 ps
  • 0x3 = > 450 ps to 600 ps
  • 0x4 = > 600 ps to 750 ps
  • 0x5 = > 750 ps to 1050 ps
  • 0x6 = Reserved
  • 0x7 = Reserved

1.640 R1133 (Offset = 0x46D)

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Table 1-642 R1133 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_6_7_SR_DDLYR/W0x0 OUT6_7 SYSREF Digital Delay Value. Measured in VCO half-cycles.
ROM=Y, EEPROM=N

1.641 R1134 (Offset = 0x46E)

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Table 1-643 R1134 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_6_7_SR_DIV_19:16R/W0x0 See Register 1136

1.642 R1135 (Offset = 0x46F)

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Table 1-644 R1135 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_6_7_SR_DIV_15:8R/W0x0 See Register 1136

1.643 R1136 (Offset = 0x470)

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Table 1-645 R1136 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_6_7_SR_DIVR/W0x0 OUT6_7 SYSREF Divide Value.
ROM=Y, EEPROM=N

1.644 R1137 (Offset = 0x471)

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Table 1-646 R1137 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0OUT_6_7_SR_DIV_STATIC_OFFSET_14:8R/W0x0 See Register 1138

1.645 R1138 (Offset = 0x472)

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Table 1-647 R1138 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_6_7_SR_DIV_STATIC_OFFSETR/W0x0 OUT_6_7_SR_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization
ROM=Y, EEPROM=N

1.646 R1139 (Offset = 0x473)

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Table 1-648 R1139 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_6_7_SR_REQ_MODER/W0x0 OUT6_7 SYSREF Mute Enable
ROM=Y, EEPROM=N
5:3OUT_6_7_PULSE_COUNTR/W0x0 OUT6_7 SYSREF Pulse Count. The number of SYSREF pulses which will be generated by a SYSREF request.
ROM=Y, EEPROM=N
2OUT_6_7_SR_GPIO_ENR/W0x0 Enables SYSREF to digital for SYSREF request resampling, continuous SYSREF, or 1-PPS GPIO output. Only one OUT_x_y_SR_GPIO_EN should be enabled at a time.
ROM=Y, EEPROM=N
1:0OUT_6_7_SR_MODER/W0x0 OUT6_7 SYSREF Mode. When these bits are set, the SYSREF operates in Continuous Mode. When cleared, the SYSREF operates in PULSE MODE.
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = Continuous
  • 0x2 = Pulser

1.647 R1140 (Offset = 0x474)

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Table 1-649 R1140 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:5RESERVEDR0x0 Reserved
4OUT_6_7_SR_CH_DIV_BYPASSR/W0x0 OUT6_7 cascaded SYSREF bypass mux. If set, bypasses OUT6_7 channel divider for the SYSREF input clock. This is useful for minimizing the step size of the digital delay adjustments on the SYSREF clock.
ROM=Y, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.648 R1153 (Offset = 0x481)

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Table 1-650 R1153 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_8_ENR/W0x1 OUT8 Enable.
ROM=Y, EEPROM=Y
5:0OUT_8_FMTR/W0x0 Remix of OUT_8_VOD and OUT_8_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.649 R1154 (Offset = 0x482)

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Table 1-651 R1154 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_8_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_8_CONFIGURATIONR/W0x0 OUT8 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.650 R1155 (Offset = 0x483)

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Table 1-652 R1155 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_9_ENR/W0x1 OUT9 Enable.
ROM=Y, EEPROM=Y
5:0OUT_9_FMTR/W0x0 Remix of OUT_9_VOD and OUT_9_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.651 R1156 (Offset = 0x484)

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Table 1-653 R1156 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_9_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_9_CONFIGURATIONR/W0x0 OUT9 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.652 R1157 (Offset = 0x485)

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Table 1-654 R1157 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_8_9_DIV_SYNC_ENR/W0x0 OUT8_9 Divider Sync Enable. Enables synchronization of chandiv dividers for OUT8_9.
ROM=Y, EEPROM=N
4OUT_8_9_SR_DIV_SYNC_ENR/W0x0 OUT8_9 SYSREF Divider Sync Enable. Enables synchronization of SYSREF dividers for OUT8_9.
ROM=Y, EEPROM=N
3:2RESERVEDR0x0 Reserved
1OUT_8_9_CHAN_POL_SELR/W0x0 OUT8_9 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
0OUT_8_9_DIV_ENR/W0x0 OUT8_9 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y

1.653 R1158 (Offset = 0x486)

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Table 1-655 R1158 Field Descriptions
BitFieldTypeResetDescription
7OUT_8_9_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
6RESERVEDR0x0 Reserved
5OUT_8_9_CLK_IN_SELR/W0x0 OUT8_9 Input Clock Select. Selects the input clock which will be used to drive the output: 0 = VCO2, 1 = VCO3
ROM=Y, EEPROM=Y
  • 0x0 = PLL2
  • 0x1 = PLL3
4OUT_8_9_CH_DIV_SR_MUX_CLK_SELR/W0x0 OUT8_9 ChanDiv to SYSREF Clock Select. When set, the channel divider output is inverted before being fed to the SYSREF.
ROM=Y, EEPROM=N
3:0OUT_8_9_CH_MUX_SELR/W0x0 OUT8_9 Input Clock Enable. Enables the selected clock to various inputs: [0] -> ChanDiv, [1] -> ChanDiv Retimer, [2] -> Div2 to OUT8, [3] -> Div2 to OUT9
ROM=Y, EEPROM=Y
  • 0x0 = OFF
  • 0x1 = SYSREF
  • 0x3 = CHDIV
  • 0x4 = DIV2->OUT8
  • 0x5 = DIV2->OUT8, SYSREF->OUT9
  • 0x7 = DIV2->OUT8, CHDIV->OUT9
  • 0x8 = DIV2->OUT9
  • 0x9 = SYSREF->OUT8, DIV2->OUT9
  • 0xB = CHDIV->OUT8, DIV2->OUT9
  • 0xC = DIV2->OUT8, DIV2->OUT9

1.654 R1159 (Offset = 0x487)

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Table 1-656 R1159 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_8_9_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1160

1.655 R1160 (Offset = 0x488)

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Table 1-657 R1160 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_8_9_CH_STATIC_OFFSETR/W0x0 OUT_8_9_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.656 R1161 (Offset = 0x489)

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Table 1-658 R1161 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_8_9_CH_DIV_11:8R/W0x0 See Register 1162

1.657 R1162 (Offset = 0x48A)

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Table 1-659 R1162 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_8_9_CH_DIVR/W0x0 OUT8_9 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.658 R1163 (Offset = 0x48B)

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Table 1-660 R1163 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_8_9_SR_ANA_DELAYR/W0x0 OUT8_9 SYSREF Analog Delay. Specified here in multiples of one delay step duration.
ROM=Y, EEPROM=N

1.659 R1164 (Offset = 0x48C)

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Table 1-661 R1164 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_8_9_SR_ANA_DELAY_DIV2_SELR/W0x0 OUT8_9 SYSREF Analog Delay Div By 2 Select. Divides the incoming clock by 2 to double the delay step size. Useful for increasing analog delay range, given high incoming clock frequencies.
ROM=Y, EEPROM=N
4OUT_8_9_SR_ANA_DELAY_ENR/W0x0 OUT8_9 SYSREF Analog Delay Enable. Enables the analog delay generator. Set to a 0 to save power if analog delay generator is not needed.
ROM=Y, EEPROM=N
3OUT_8_9_SR_ANA_DELAY_SMALL_STEP_ENR/W0x0 OUT8_9 SYSREF Analog Delay Small Step Enable. If set to 1, the analog delay generator will use both rising and falling edges of the incoming clock to halve delay step size. Useful for when large pre-divider values have been used.
ROM=Y, EEPROM=N
2:0OUT_8_9_SR_ANA_DELAY_RANGER/W0x0 Analog delay range is set according to the period entering the SYSREF analog delay block. The period can be calculated as (OUT_x_y_SR_ANA_DELAY_DIV2_SEL + 1) / (OUT_x_y_SR_ANA_DELAY_SMALL_STEP_EN + 1) / VCO post divider frequency. Calculated range must fall between 333 ps and 1050 ps.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = 333 ps to 450 ps
  • 0x3 = > 450 ps to 600 ps
  • 0x4 = > 600 ps to 750 ps
  • 0x5 = > 750 ps to 1050 ps
  • 0x6 = Reserved
  • 0x7 = Reserved

1.660 R1165 (Offset = 0x48D)

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Table 1-662 R1165 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_8_9_SR_DDLYR/W0x0 OUT8_9 SYSREF Digital Delay Value. Measured in VCO half-cycles.
ROM=Y, EEPROM=N

1.661 R1166 (Offset = 0x48E)

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Table 1-663 R1166 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_8_9_SR_DIV_19:16R/W0x0 See Register 1168

1.662 R1167 (Offset = 0x48F)

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Table 1-664 R1167 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_8_9_SR_DIV_15:8R/W0x0 See Register 1168

1.663 R1168 (Offset = 0x490)

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Table 1-665 R1168 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_8_9_SR_DIVR/W0x0 OUT8_9 SYSREF Divide Value.
ROM=Y, EEPROM=N

1.664 R1169 (Offset = 0x491)

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Table 1-666 R1169 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0OUT_8_9_SR_DIV_STATIC_OFFSET_14:8R/W0x0 See Register 1170

1.665 R1170 (Offset = 0x492)

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Table 1-667 R1170 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_8_9_SR_DIV_STATIC_OFFSETR/W0x0 OUT_8_9_SR_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization
ROM=Y, EEPROM=N

1.666 R1171 (Offset = 0x493)

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Table 1-668 R1171 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_8_9_SR_REQ_MODER/W0x0 OUT8_9 SYSREF Mute Enable
ROM=Y, EEPROM=N
5:3OUT_8_9_PULSE_COUNTR/W0x0 OUT8_9 SYSREF Pulse Count. The number of SYSREF pulses which will be generated by a SYSREF request.
ROM=Y, EEPROM=N
2OUT_8_9_SR_GPIO_ENR/W0x0 Enables SYSREF to digital for SYSREF request resampling, continuous SYSREF, or 1-PPS GPIO output. Only one OUT_x_y_SR_GPIO_EN should be enabled at a time.
ROM=Y, EEPROM=N
1:0OUT_8_9_SR_MODER/W0x0 OUT8_9 SYSREF Mode. When these bits are set, the SYSREF operates in Continuous Mode. When cleared, the SYSREF operates in PULSE MODE.
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = Continuous
  • 0x2 = Pulser

1.667 R1185 (Offset = 0x4A1)

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Table 1-669 R1185 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_10_ENR/W0x1 OUT10 Enable.
ROM=Y, EEPROM=Y
5:0OUT_10_FMTR/W0x0 Remix of OUT_10_VOD and OUT_10_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.668 R1186 (Offset = 0x4A2)

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Table 1-670 R1186 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_10_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_10_CONFIGURATIONR/W0x0 OUT10 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.669 R1187 (Offset = 0x4A3)

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Table 1-671 R1187 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_11_ENR/W0x1 OUT11 Enable.
ROM=Y, EEPROM=Y
5:0OUT_11_FMTR/W0x0 Remix of OUT_11_VOD and OUT_11_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.670 R1188 (Offset = 0x4A4)

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Table 1-672 R1188 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_11_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_11_CONFIGURATIONR/W0x0 OUT11 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.671 R1189 (Offset = 0x4A5)

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Table 1-673 R1189 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_10_11_DIV_SYNC_ENR/W0x0 OUT10_11 Divider Sync Enable. Enables synchronization of chandiv dividers for OUT10_11.
ROM=Y, EEPROM=N
4OUT_10_11_SR_DIV_SYNC_ENR/W0x0 OUT10_11 SYSREF Divider Sync Enable. Enables synchronization of SYSREF dividers for OUT10_11.
ROM=Y, EEPROM=N
3:2RESERVEDR0x0 Reserved
1OUT_10_11_CHAN_POL_SELR/W0x0 OUT10_11 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
0OUT_10_11_DIV_ENR/W0x0 OUT10_11 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y

1.672 R1190 (Offset = 0x4A6)

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Table 1-674 R1190 Field Descriptions
BitFieldTypeResetDescription
7OUT_10_11_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
6OUT_10_11_ZDM_ENR/W0x0 OUT10_11 zero delay output enable.
ROM=Y, EEPROM=N
5OUT_10_11_CLK_IN_SELR/W0x0 OUT10_11 Input Clock Select. Selects the input clock which will be used to drive the output: 0 = VCO2, 1 = VCO3
ROM=Y, EEPROM=Y
  • 0x0 = PLL2
  • 0x1 = PLL3
4OUT_10_11_CH_DIV_SR_MUX_CLK_SELR/W0x0 OUT10_11 ChanDiv to SYSREF Clock Select. When set, the channel divider output is inverted before being fed to the SYSREF.
ROM=Y, EEPROM=N
3:0OUT_10_11_CH_MUX_SELR/W0x0 OUT10_11 Input Clock Enable. Enables the selected clock to various inputs: [0] -> ChanDiv, [1] -> ChanDiv Retimer, [2] -> Div2 to OUT10, [3] -> Div2 to OUT11
ROM=Y, EEPROM=Y
  • 0x0 = OFF
  • 0x1 = SYSREF
  • 0x3 = CHDIV
  • 0x4 = DIV2->OUT10
  • 0x5 = DIV2->OUT10, SYSREF->OUT11
  • 0x7 = DIV2->OUT10, CHDIV->OUT11
  • 0x8 = DIV2->OUT11
  • 0x9 = SYSREF->OUT10, DIV2->OUT11
  • 0xB = CHDIV->OUT10, DIV2->OUT11
  • 0xC = DIV2->OUT10, DIV2->OUT11

1.673 R1191 (Offset = 0x4A7)

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Table 1-675 R1191 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_10_11_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1192

1.674 R1192 (Offset = 0x4A8)

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Table 1-676 R1192 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_10_11_CH_STATIC_OFFSETR/W0x0 OUT_10_11_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.675 R1193 (Offset = 0x4A9)

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Table 1-677 R1193 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_10_11_CH_DIV_11:8R/W0x0 See Register 1194

1.676 R1194 (Offset = 0x4AA)

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Table 1-678 R1194 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_10_11_CH_DIVR/W0x0 OUT10_11 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.677 R1195 (Offset = 0x4AB)

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Table 1-679 R1195 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_10_11_SR_ANA_DELAYR/W0x0 OUT10_11 SYSREF Analog Delay. Specified here in multiples of one delay step duration.
ROM=Y, EEPROM=N

1.678 R1196 (Offset = 0x4AC)

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Table 1-680 R1196 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_10_11_SR_ANA_DELAY_DIV2_SELR/W0x0 OUT10_11 SYSREF Analog Delay Div By 2 Select. Divides the incoming clock by 2 to double the delay step size. Useful for increasing analog delay range, given high incoming clock frequencies.
ROM=Y, EEPROM=N
4OUT_10_11_SR_ANA_DELAY_ENR/W0x0 OUT10_11 SYSREF Analog Delay Enable. Enables the analog delay generator. Set to a 0 to save power if analog delay generator is not needed.
ROM=Y, EEPROM=N
3OUT_10_11_SR_ANA_DELAY_SMALL_STEP_ENR/W0x0 OUT10_11 SYSREF Analog Delay Small Step Enable. If set to 1, the analog delay generator will use both rising and falling edges of the incoming clock to halve delay step size. Useful for when large pre-divider values have been used.
ROM=Y, EEPROM=N
2:0OUT_10_11_SR_ANA_DELAY_RANGER/W0x0 Analog delay range is set according to the period entering the SYSREF analog delay block. The period can be calculated as (OUT_x_y_SR_ANA_DELAY_DIV2_SEL + 1) / (OUT_x_y_SR_ANA_DELAY_SMALL_STEP_EN + 1) / VCO post divider frequency. Calculated range must fall between 333 ps and 1050 ps.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = 333 ps to 450 ps
  • 0x3 = > 450 ps to 600 ps
  • 0x4 = > 600 ps to 750 ps
  • 0x5 = > 750 ps to 1050 ps
  • 0x6 = Reserved
  • 0x7 = Reserved

1.679 R1197 (Offset = 0x4AD)

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Table 1-681 R1197 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_10_11_SR_DDLYR/W0x0 OUT10_11 SYSREF Digital Delay Value. Measured in VCO half-cycles.
ROM=Y, EEPROM=N

1.680 R1198 (Offset = 0x4AE)

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Table 1-682 R1198 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_10_11_SR_DIV_19:16R/W0x0 See Register 1200

1.681 R1199 (Offset = 0x4AF)

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Table 1-683 R1199 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_10_11_SR_DIV_15:8R/W0x0 See Register 1200

1.682 R1200 (Offset = 0x4B0)

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Table 1-684 R1200 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_10_11_SR_DIVR/W0x0 OUT10_11 SYSREF Divide Value.
ROM=Y, EEPROM=N

1.683 R1201 (Offset = 0x4B1)

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Table 1-685 R1201 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0OUT_10_11_SR_DIV_STATIC_OFFSET_14:8R/W0x0 See Register 1202

1.684 R1202 (Offset = 0x4B2)

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Table 1-686 R1202 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_10_11_SR_DIV_STATIC_OFFSETR/W0x0 OUT_10_11_SR_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization
ROM=Y, EEPROM=N

1.685 R1203 (Offset = 0x4B3)

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Table 1-687 R1203 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_10_11_SR_REQ_MODER/W0x0 OUT10_11 SYSREF Mute Enable
ROM=Y, EEPROM=N
5:3OUT_10_11_PULSE_COUNTR/W0x0 OUT10_11 SYSREF Pulse Count. The number of SYSREF pulses which will be generated by a SYSREF request.
ROM=Y, EEPROM=N
2OUT_10_11_SR_GPIO_ENR/W0x0 Enables SYSREF to digital for SYSREF request resampling, continuous SYSREF, or 1-PPS GPIO output. Only one OUT_x_y_SR_GPIO_EN should be enabled at a time.
ROM=Y, EEPROM=N
1:0OUT_10_11_SR_MODER/W0x0 OUT10_11 SYSREF Mode. When these bits are set, the SYSREF operates in Continuous Mode. When cleared, the SYSREF operates in PULSE MODE.
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = Continuous
  • 0x2 = Pulser

1.686 R1204 (Offset = 0x4B4)

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Table 1-688 R1204 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:5RESERVEDR0x0 Reserved
4OUT_10_11_SR_CH_DIV_BYPASSR/W0x0 OUT10_11 cascaded SYSREF bypass mux. If set, bypasses OUT10_11 channel divider for the SYSREF input clock. This is useful for minimizing the step size of the digital delay adjustments on the SYSREF clock.
ROM=Y, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.687 R1217 (Offset = 0x4C1)

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Table 1-689 R1217 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_12_ENR/W0x1 OUT12 Enable.
ROM=Y, EEPROM=Y
5:0OUT_12_FMTR/W0x0 Remix of OUT_12_VOD and OUT_12_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.688 R1218 (Offset = 0x4C2)

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Table 1-690 R1218 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_12_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_12_CONFIGURATIONR/W0x0 OUT12 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.689 R1219 (Offset = 0x4C3)

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Table 1-691 R1219 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_13_ENR/W0x1 OUT13 Enable.
ROM=Y, EEPROM=Y
5:0OUT_13_FMTR/W0x0 Remix of OUT_13_VOD and OUT_13_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.690 R1220 (Offset = 0x4C4)

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Table 1-692 R1220 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_13_CAP_ENR/W0x1 ROM=Y, EEPROM=N
5RESERVEDR0x0 Reserved
4:0OUT_13_CONFIGURATIONR/W0x0 OUT13 configuration.
ROM=Y, EEPROM=Y and N
  • 0x0 = CH/2
  • 0x8 = SYSREF+ADLY
  • 0x9 = SYSREF
  • 0xA = Static DC
  • 0xC = CHDIV
  • 0x10 = BYPASS

1.691 R1221 (Offset = 0x4C5)

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Table 1-693 R1221 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_12_13_DIV_SYNC_ENR/W0x0 OUT12_13 Divider Sync Enable. Enables synchronization of chandiv dividers for OUT12_13.
ROM=Y, EEPROM=N
4OUT_12_13_SR_DIV_SYNC_ENR/W0x0 OUT12_13 SYSREF Divider Sync Enable. Enables synchronization of SYSREF dividers for OUT12_13.
ROM=Y, EEPROM=N
3:2RESERVEDR0x0 Reserved
1OUT_12_13_CHAN_POL_SELR/W0x0 OUT12_13 ChanDiv Polarity Select. When cleared, this bit inverts the polarity of the input to the channel divider.
ROM=Y, EEPROM=N
0OUT_12_13_DIV_ENR/W0x0 OUT12_13 ChanDiv Enable. Enables the channel divider. Note: SYSREF/chandiv mode must be configured separately.
ROM=Y, EEPROM=Y

1.692 R1222 (Offset = 0x4C6)

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Table 1-694 R1222 Field Descriptions
BitFieldTypeResetDescription
7OUT_12_13_MUTE_ENR/W0x0 Mute enable.
ROM=Y, EEPROM=N
6RESERVEDR0x0 Reserved
5OUT_12_13_CLK_IN_SELR/W0x0 OUT12_13 Input Clock Select. Selects the input clock which will be used to drive the output. For crosstlak performance OUT8 to OUT13 should select the same VCO souce: 0 = VCO2, 1 = VCO3.
ROM=Y, EEPROM=Y
  • 0x0 = PLL2
  • 0x1 = PLL3
4OUT_12_13_CH_DIV_SR_MUX_CLK_SELR/W0x0 OUT12_13 ChanDiv to SYSREF Clock Select. When set, the channel divider output is inverted before being fed to the SYSREF.
ROM=Y, EEPROM=N
3:0OUT_12_13_CH_MUX_SELR/W0x0 OUT12_13 Input Clock Enable. Enables the selected clock to various inputs: [0] -> ChanDiv, [1] -> ChanDiv Retimer, [2] -> Div2 to OUT12, [3] -> Div2 to OUT13
ROM=Y, EEPROM=Y
  • 0x0 = OFF
  • 0x1 = SYSREF
  • 0x3 = CHDIV
  • 0x4 = DIV2->OUT12
  • 0x5 = DIV2->OUT12, SYSREF->OUT13
  • 0x7 = DIV2->OUT12, CHDIV->OUT13
  • 0x8 = DIV2->OUT13
  • 0x9 = SYSREF->OUT12, DIV2->OUT13
  • 0xB = CHDIV->OUT12, DIV2->OUT13
  • 0xC = DIV2->OUT12, DIV2->OUT13

1.693 R1223 (Offset = 0x4C7)

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Table 1-695 R1223 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_12_13_CH_STATIC_OFFSET_11:8R/W0x0 See Register 1224

1.694 R1224 (Offset = 0x4C8)

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Table 1-696 R1224 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_12_13_CH_STATIC_OFFSETR/W0x0 OUT_12_13_CH_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization. Lower 8 bits are stored in EEPROM.
ROM=Y, EEPROM=Y

1.695 R1225 (Offset = 0x4C9)

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Table 1-697 R1225 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_12_13_CH_DIV_11:8R/W0x0 See Register 1226

1.696 R1226 (Offset = 0x4CA)

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Table 1-698 R1226 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_12_13_CH_DIVR/W0x0 OUT12_13 ChanDiv Divide Value.
ROM=Y, EEPROM=Y

1.697 R1227 (Offset = 0x4CB)

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Table 1-699 R1227 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_12_13_SR_ANA_DELAYR/W0x0 OUT12_13 SYSREF Analog Delay. Specified here in multiples of one delay step duration.
ROM=Y, EEPROM=N

1.698 R1228 (Offset = 0x4CC)

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Table 1-700 R1228 Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDR0x0 Reserved
5OUT_12_13_SR_ANA_DELAY_DIV2_SELR/W0x0 OUT12_13 SYSREF Analog Delay Div By 2 Select. Divides the incoming clock by 2 to double the delay step size. Useful for increasing analog delay range, given high incoming clock frequencies.
ROM=Y, EEPROM=N
4OUT_12_13_SR_ANA_DELAY_ENR/W0x0 OUT12_13 SYSREF Analog Delay Enable. Enables the analog delay generator. Set to a 0 to save power if analog delay generator is not needed.
ROM=Y, EEPROM=N
3OUT_12_13_SR_ANA_DELAY_SMALL_STEP_ENR/W0x0 OUT12_13 SYSREF Analog Delay Small Step Enable. If set to 1, the analog delay generator will use both rising and falling edges of the incoming clock to halve delay step size. Useful for when large pre-divider values have been used.
ROM=Y, EEPROM=N
2:0OUT_12_13_SR_ANA_DELAY_RANGER/W0x0 Analog delay range is set according to the period entering the SYSREF analog delay block. The period can be calculated as (OUT_x_y_SR_ANA_DELAY_DIV2_SEL + 1) / (OUT_x_y_SR_ANA_DELAY_SMALL_STEP_EN + 1) / VCO post divider frequency. Calculated range must fall between 333 ps and 1050 ps.
ROM=Y, EEPROM=N
  • 0x0 = Reserved
  • 0x1 = Reserved
  • 0x2 = 333 ps to 450 ps
  • 0x3 = > 450 ps to 600 ps
  • 0x4 = > 600 ps to 750 ps
  • 0x5 = > 750 ps to 1050 ps
  • 0x6 = Reserved
  • 0x7 = Reserved

1.699 R1229 (Offset = 0x4CD)

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Table 1-701 R1229 Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDR0x0 Reserved
4:0OUT_12_13_SR_DDLYR/W0x0 OUT12_13 SYSREF Digital Delay Value. Measured in VCO half-cycles.
ROM=Y, EEPROM=N

1.700 R1230 (Offset = 0x4CE)

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Table 1-702 R1230 Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDR0x0 Reserved
3:0OUT_12_13_SR_DIV_19:16R/W0x0 See Register 1232

1.701 R1231 (Offset = 0x4CF)

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Table 1-703 R1231 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_12_13_SR_DIV_15:8R/W0x0 See Register 1232

1.702 R1232 (Offset = 0x4D0)

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Table 1-704 R1232 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_12_13_SR_DIVR/W0x0 OUT12_13 SYSREF Divide Value.
ROM=Y, EEPROM=N

1.703 R1233 (Offset = 0x4D1)

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Table 1-705 R1233 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:0OUT_12_13_SR_DIV_STATIC_OFFSET_14:8R/W0x0 See Register 1234

1.704 R1234 (Offset = 0x4D2)

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Table 1-706 R1234 Field Descriptions
BitFieldTypeResetDescription
7:0OUT_12_13_SR_DIV_STATIC_OFFSETR/W0x0 OUT_12_13_SR_DIV static digital delay value. Delays divider start by specified number of full clock cycles of divider input. This results in specified digital delay upon divider synchronization
ROM=Y, EEPROM=N

1.705 R1235 (Offset = 0x4D3)

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Table 1-707 R1235 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6OUT_12_13_SR_REQ_MODER/W0x0 OUT12_13 SYSREF Mute Enable
ROM=Y, EEPROM=N
5:3OUT_12_13_PULSE_COUNTR/W0x0 OUT12_13 SYSREF Pulse Count. The number of SYSREF pulses which will be generated by a SYSREF request.
ROM=Y, EEPROM=N
2OUT_12_13_SR_GPIO_ENR/W0x0 Enables SYSREF to digital for SYSREF request resampling, continuous SYSREF, or 1-PPS GPIO output. Only one OUT_x_y_SR_GPIO_EN should be enabled at a time.
ROM=Y, EEPROM=N
1:0OUT_12_13_SR_MODER/W0x0 OUT12_13 SYSREF Mode. When these bits are set, the SYSREF operates in Continuous Mode. When cleared, the SYSREF operates in PULSE MODE.
ROM=Y, EEPROM=N
  • 0x0 = None
  • 0x1 = Continuous
  • 0x2 = Pulser

1.706 R1236 (Offset = 0x4D4)

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Table 1-708 R1236 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6:5RESERVEDR0x0 Reserved
4OUT_12_13_SR_CH_DIV_BYPASSR/W0x0 OUT12_13 cascaded SYSREF bypass mux. If set, bypasses OUT12_13 channel divider for the SYSREF input clock. This is useful for minimizing the step size of the digital delay adjustments on the SYSREF clock.
ROM=Y, EEPROM=N
3:0RESERVEDR0x0 Reserved

1.707 R1248 (Offset = 0x4E0)

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Table 1-709 R1248 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5:0OUT_14_FMTR/W0x0 Remix of OUT_14_VOD and OUT_14_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

1.708 R1280 (Offset = 0x500)

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Table 1-710 R1280 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0x0 Reserved
6RESERVEDR0x0 Reserved
5:0OUT_15_FMTR/W0x0 Remix of OUT_15_VOD and OUT_15_VOS to display datasheet specified settings availible to user.
ROM=Y, EEPROM=Y
  • 0x8 = HSDS 400 mV, Vcm = 0.35 V
  • 0x9 = HSDS 500 mV, Vcm = 0.4 V
  • 0xA = HSDS 600 mV, Vcm = 0.45 V
  • 0xB = HSDS 700 mV, Vcm = 0.5 V
  • 0xC = HSDS 800 mV, Vcm = 0.55 V
  • 0xD = HSDS 900 mV, Vcm = 0.6 V
  • 0xE = HSDS 1000 mV, Vcm = 0.65 V
  • 0xF = HCSL 750 mV (fast)
  • 0x10 = HSDS 400 mV, Vcm = 0.7 V
  • 0x20 = LVDS, Vcm = 1.25 V
  • 0x32 = HSDS 600 mV, Vcm = 0.8 V
  • 0x33 = HSDS 700 mV, Vcm = 0.9 V
  • 0x34 = HSDS 800 mV, Vcm = 1 V
  • 0x4F = HCSL 750 mV

 
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