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  • ISO7842x 高性能、8000VPK 增强型四通道数字隔离器

    • ZHCSD14G October   2014  – March 2017 ISO7842

      PRODUCTION DATA.  

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  • ISO7842x 高性能、8000VPK 增强型四通道数字隔离器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics-5-V Supply
    10. 6.10 Supply Current Characteristics-5-V Supply
    11. 6.11 Electrical Characteristics—3.3-V Supply
    12. 6.12 Supply Current Characteristics—3.3-V Supply
    13. 6.13 Electrical Characteristics—2.5-V Supply
    14. 6.14 Supply Current Characteristics—2.5-V Supply
    15. 6.15 Switching Characteristics—5-V Supply
    16. 6.16 Switching Characteristics—3.3-V Supply
    17. 6.17 Switching Characteristics—2.5-V Supply
    18. 6.18 Insulation Characteristics Curves
    19. 6.19 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Electromagnetic Compatibility (EMC) Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device I/O Schematics
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 PCB Material
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 相关链接
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

ISO7842x 高性能、8000VPK 增强型四通道数字隔离器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 信号传输速率：高达 100Mbps
  • 宽电源电压范围：2.25V 至 5.5V
  • 2.25V 至 5.5V 电平转换
  • 宽温度范围：–55°C 至 +125°C
  • 低功耗：电流典型值为 1.7mA/通道（1Mbps 时）
  • 低传播延迟：典型值为 11ns
    （5V 电源供电时）
  • 行业领先的 CMTI（最小值）：±100 kV/μs
  • 优异的电磁兼容性 (EMC)
  • 系统级静电放电 (ESD)、瞬态放电 (EFT) 以及抗浪涌保护
  • 低辐射
  • 隔离层寿命：40 年以上
  • 宽体 SOIC-16 封装和超宽体 SOIC-16 封装选项
  • 安全及管理批准：中的“安全及管理批准”列表中的“安全及管理批准”列表
    • 8000 VPK 增强型隔离，符合 DIN V VDE V 0884-10 (VDE V 0884-10)：2006-12
    • 符合 UL 1577 标准且长达 1 分钟的 5.7kVRMS 隔离
    • CSA 组件验收通知 5A，IEC 60950-1 和 IEC 60601-1 终端设备标准
    • 符合 GB4943.1-2011 标准的 CQC 认证
    • 符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证
    • 完成了所有 DW 封装认证；完成了符合 UL、VDE、TUV 标准的 DWW 封装认证并且已针对 CSA 和 CQC 进行了规划

2 应用

  • 工业自动化
  • 电机控制
  • 电源
  • 太阳能逆变器
  • 医疗设备
  • 混合动力电动汽车

3 说明

ISO7842x 器件是一款高性能四通道数字隔离器，隔离电压为 8000VPK。该器件已通过符合 VDE、CSA、CQC 和 TUV 标准的增强型隔离认证。在隔离互补金属氧化物半导体 (CMOS) 或者低电压互补金属氧化物半导体 (LVCMOS) 数字 I/O 时，该隔离器可提供高电磁抗扰度和低辐射，同时具备低功耗特性。每个隔离通道都有一个由二氧化硅 (SiO2) 绝缘隔栅分开的逻辑输入和输出缓冲器。

该器件配有使能引脚，可用于将多个主驱动应用中的相应输出置于 高阻抗状态， 也可用于降低功耗。ISO7842 器件具有 2 个正向通道和 2 个反向通道。如果出现输入功率或信号丢失，ISO7842 器件默认输出高电平，ISO7842F 器件默认输出低电平。有关更多详细信息，请参阅 Device Functional Modes器件功能模式部分。

与隔离式电源结合使用时，该器件有助于防止数据总线或者其他电路中的噪声电流进入本地接地，进而干扰或损坏敏感电路。凭借创新的芯片设计和布线技术，ISO7842 器件的电磁兼容性得到了显著增强，可确保提供系统级 ESD、EFT 和浪涌保护并符合辐射标准。

ISO7842 器件采用 16 引脚 SOIC 宽体 (DW) 和超宽体 (DWW) 封装。

器件信息(1)

产品型号 封装 封装尺寸（标称值）
ISO7842
ISO7842F		 DW (16) 10.30mm x 7.50mm
DWW (16) 10.30mm x 14.0mm
  1. 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。

简化电路原理图

ISO7842 ISO7842F Simplified_Schematic_sllsei6.gif
VCCI 和 GNDI 分别是输入通道的电源和接地连接。
VCCO 和 GNDO 分别是输出通道的电源和接地连接。

4 修订历史记录

Changes from F Revision (April 2016) to G Revision

  • Changed part numbers in the Power Ratings table (previously Power Dissipation Characteristics) Go
  • Changed the input-to-output test voltage parameter to apparent charge in the Insulation Specifications Go
  • Added 接收文档更新通知部分Go

Changes from E Revision (March 2016) to F Revision

  • Changed 隔离层寿命年数（特性部分）Go
  • VDE 认证现在已完成Go
  • Changed VCCO to VCCI for the minimum value of the input threshold voltage hysteresis parameter in all electrical characteristics tablesGo
  • Added VCM to the test condition of the common-mode transient immunity parameter in all electrical characteristics tablesGo
  • Added the lifetime projection graphs for DW and DWW packages to the Safety Limiting Values section Go

Changes from D Revision (December 2015) to E Revision

  • 更改了特性Go
  • 在特性中添加了“符合 EN 61010-1 和 EN 60950-1 标准的 TUV 认证”Go
  • 将说明的第一段中的文本从“符合 VDE、CSA 和 CQC 的认证” 更改为“符合 VDE、CSA、CQC 和 TUV 的认证。”Go
  • Added Note 1 to Insulation Characteristics Go
  • Changed IEC 60664-1 Ratings TableGo
  • Added TUV to the Regulatory Information section and Regulatory Information. Deleted Note 1 in Regulatory Information Go
  • Changed Device I/O Schematics Go

Changes from C Revision (July 2015) to D Revision

  • 在特性中添加了“完成了 DW 封装认证；规划了 DWW 认证”Go
  • 向说明部分添加了文本：“和超宽体 (DWW) 封装”。Go
  • 已将封装“超宽 SOIC、DWW (16)”添加至器件信息表Go
  • Added the 16-DWW Package to Package Insulation and Safety-Related SpecificationsGo
  • Added the DWW package information to Package Insulation and Safety-Related SpecificationsGo
  • Added the DWW package information to Regulatory InformationGo
  • Changed the MIN value of CMTI in Electrical Characteristics–5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted the TYP value of 100 kV/μsGo
  • Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics–5-V SupplyGo
  • Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics–5-V SupplyGo
  • Changed the MIN value of CMTI in Electrical Characteristics—3.3-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted the TYP value of 100 kV/μsGo
  • Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—3.3-V SupplyGo
  • Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—3.3-V SupplyGo
  • Changed the MIN value of CMTI in Electrical Characteristics—2.5-V Supply, 5 V table From: 70 To: 100 kV/μs, deleted the TYP value of 100 kV/μsGo
  • Added the Supply Current - ISO7842DW and ISO7842FDW section to the Supply Current Characteristics—2.5-V SupplyGo
  • Added the Supply Current - ISO7842DWW and ISO7842FDWW section to the Supply Current Characteristics—2.5-V SupplyGo
  • Added text to the Application Information section: " isolation voltage per UL 1577." Go

Changes from B Revision (April 2015) to C Revision

  • 已添加器件 ISO7482F 至数据表Go
  • 已更改 说明以包含“ISO7842 器件默认输出为“高”，ISO7842F 器件默认输出为“低””。Go
  • Changed Thermal Derating Curve for Safety Limiting Current per VDE , Added Thermal Derating Curve for Safety Limiting Power per VDEGo
  • Changed From: tPLH and tPHLat 5.5V To: tPLH and tPHL at 5.0 V Go
  • Changed Default Output Delay Time Test Circuit and Voltage WaveformsGo
  • Added the Device I/O Schematics section Go

Changes from A Revision (November 2014) to B Revision

  • 已将文档标题从“四通道数字隔离器”更改为“四通道 2/2 数字隔离器”Go
  • 在特性部分添加了“2.25V 至 5.5V 电平转换”Go
  • 将特性中的“宽体 SOIC-16 封装”更改为“宽体和超宽体 SOIC-16 封装选项”Go
  • 更改了特性Go
  • VDE 认证现在已完成Go
  • 更改了简化电路原理图并增加了注释 1 和注释 2Go
  • Added the Power Dissipation Characteristics tableGo
  • Changed Package Insulation and Safety-Related SpecificationsGo
  • Changed Insulation Characteristics title From: DIN V VDE 0884-10 (VDE V 0884-10) and UL 1577 Insulation Characteristics To: Insulation CharacteristicsGo
  • Changed Insulation Characteristics Go
  • Changed the Test Condition of CTI of the table in Package Insulation and Safety-Related Specifications Go
  • Changed the MIN value of CTI From" > 600 V To: 600 V Go
  • Changed the table in Regulatory InformationGo
  • Changed Switching Characteristics Test Circuit and Voltage Waveforms Go
  • Changed Enable/Disable Propagation Delay Time Test Circuit and Waveform Go
  • Changed From: VCC1 To: VCCI in Default Output Delay Time Test Circuit and Voltage WaveformsGo
  • Changed Common-Mode Transient Immunity Test CircuitGo
  • Deleted INPUT-SIDE and OUTPUT-SIDE from columns 1 and 2 of Function Table Go
  • Changed the Application Information section Go
  • Changed the Application Information section Go
  • Added text and typical circuit hook-up figure to the Detailed Design Procedure section Go

Changes from * Revision (October 2014) to A Revision

  • 将“特性”中的“所有机构批准待定”更改为“所有机构批准已规划”Go
  • 将 说明 部分的语句从“该器件已通过 VDE 和 CSA 认证，满足增强型隔离要求。” 更改为“该器件正在就是否满足增强型隔离要求进行 VDE 和 CSA 审核认证。”Go
  • Changed RIO MIN value From: 109 To: 1011 in the Package Insulation and Safety-Related Specifications table Go
  • Changed the first row of information in the Regulatory Information table Go

5 Pin Configuration and Functions

DW and DWW Packages
16-Pin SOIC
Top View
ISO7842 ISO7842F Po_sllsej0.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
EN1 7 I Output enable 1. Output pins on side 1 are enabled when EN1 is high or open and in high-impedance state when EN1 is low.
EN2 10 I Output enable 2. Output pins on side 2 are enabled when EN2 is high or open and in high-impedance state when EN2 is low.
GND1 2 — Ground connection for VCC1
8
GND2 9 — Ground connection for VCC2
15
INA 3 I Input, channel A
INB 4 I Input, channel B
INC 12 I Input, channel C
IND 11 I Input, channel D
OUTA 14 O Output, channel A
OUTB 13 O Output, channel B
OUTC 5 O Output, channel C
OUTD 6 O Output, channel D
VCC1 1 — Power supply, VCC1
VCC2 16 — Power supply, VCC2

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
VCC1,
VCC2 		Supply voltage(2) –0.5 6 V
Voltage INx –0.5 VCCX + 0.5(3) V
OUTx –0.5 VCCX + 0.5(3)
ENx –0.5 VCCX + 0.5(3)
IO Output current –15 15 mA
Surge immunity 12.8 kV
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak voltage values.
(3) Maximum voltage must not exceed 6 V

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±6000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC1, VCC2 Supply voltage 2.25 5.5 V
IOH High-level output current VCCO(2) = 5 V –4 mA
VCCO(2) = 3.3 V –2
VCCO(2) = 2.5 V –1
IOL Low-level output current VCCO(2) = 5 V 4 mA
VCCO(2) = 3.3 V 2
VCCO(2) = 2.5 V 1
VIH High-level input voltage 0.7 × VCCI (2) VCCI (2) V
VIL Low-level input voltage 0 0.3 × VCCI(2) V
DR Signaling rate 0 100 Mbps
TJ Junction temperature(1) –55 150 °C
TA Ambient temperature –55 25 125 °C
(1) To maintain the recommended operating conditions for TJ, see Thermal Information.
(2) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.4 Thermal Information

ISO7842 UNIT
THERMAL METRIC(1) DW (SOIC) DWW (SOIC)
16 Pins 16 Pins
RθJA Junction-to-ambient thermal resistance 78.9 78.9 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 41.6 41.1 °C/W
RθJB Junction-to-board thermal resistance 43.6 49.5 °C/W
ψJT Junction-to-top characterization parameter 15.5 15.2 °C/W
ψJB Junction-to-board characterization parameter 43.1 48.8 °C/W
RθJC(bottom) Junction-to-case(bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Power Ratings

VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, input a 50 MHz 50% duty cycle square wave
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PD Maximum power dissipation by ISO7842x 200 mW
PD1 Maximum power dissipation by side-1 of ISO7842x 100 mW
PD2 Maximum power dissipation by side-2 of ISO7842x 100 mW

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
DW DWW
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air >8 >14.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surfaceHigh Voltage Feature Description >8 >14.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 >21 μm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112; UL 746A >600 >600 V
Material group I I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 600 VRMS I–IV I–IV
Rated mains voltage ≤ 1000 VRMS I–III I–IV
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12(2)
VIORM Maximum repetitive peak isolation voltage 2121 2828 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); Time dependent dielectric breakdown (TDDB) Test, see Figure 1 and Figure 2 1500 2000 VRMS
DC voltage 2121 2828 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM
t = 60 s (qualification)
t= 1 s (100% production)		 8000 8000 VPK
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50 µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)		 8000 8000 VPK
qpd Apparent charge(4) Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM = 2545 VPK (DW) and 3394 VPK (DWW), tm = 10 s		 ≤5 ≤5 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM = 3394 VPK (DW) and 4525 VPK (DWW), tm = 10 s		 ≤5 ≤5
Method b1: At routine test (100% production) and preconditioning (type test)
Vini = VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM = 3977 VPK (DW) and 5303 VPK (DWW), tm = 1 s		 ≤5 ≤5
CIO Barrier capacitance, input to output(5) VIO = 0.4 × sin (2πft), f = 1 MHz 2 2 pF
RIO Isolation resistance, input to output(5) VIO = 500 V, TA = 25°C >1012 >1012 Ω
VIO = 500 V, 100°C ≤ TA ≤ 125°C >1011 >1011
VIO = 500 V at TS = 150°C >109 >109
Pollution degree 2 2
Climatic category 55/125/21 55/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 5700 VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6840 VRMS, t = 1 s (100% production)		 5700 5700 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

Certifications for the DW package are complete. DWW package certifications are complete for UL, VDE and TUV and planned for CSA and CQC.
VDE CSA UL CQC TUV
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01 Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1 Certified according to UL 1577 Component Recognition Program Certified according to GB 4943.1-2011 Certified according to
EN 61010-1:2010 (3rd Ed) and
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013
Reinforced insulation
Maximum transient isolation voltage, 8000 VPK;
Maximum repetitive peak isolation voltage, 2121 VPK (DW), 2828 VPK (DWW);
Maximum surge isolation voltage, 8000 VPK		 Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed., 800 VRMS (DW package) and 1450 VRMS (DWW package) max working voltage (pollution degree 2, material group I);
2 MOPP (Means of Patient Protection) per CSA 60601-1:14 and IEC 60601-1 Ed. 3.1, 250 VRMS (354 VPK) max working voltage (DW package)		 Single protection, 5700 VRMS Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage 5700 VRMS Reinforced insulation per
EN 61010-1:2010 (3rd Ed) up to working voltage of 600 VRMS (DW package) and 1000 VRMS (DWW package)
5700 VRMS Reinforced insulation per
EN 60950-1:2006/A11:2009/A1:2010/
A12:2011/A2:2013 up to working voltage of 800 VRMS (DW package) and 1450 VRMS (DWW package)
Certificate number: 40040142 Master contract number: 220991 File number: E181974 Certificate number: CQC15001121716 Client ID number: 77311

6.8 Safety Limiting Values

Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current RθJA = 78.9°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C 288 mA
RθJA = 78.9°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C 440
RθJA = 78.9°C/W, VI = 2.75 V, TJ = 150°C, TA = 25°C 576
PS Safety input, output, or total power RθJA = 78.9°C/W, TJ = 150°C, TA = 25°C 1584 mW
TS Maximum safety temperature 150 °C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information is that of a device installed on a high-K test board for leaded surface-mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics–5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –4 mA; see Figure 11 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 4 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI (1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx -10
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V, VCM = 1500 V; see Figure 14 100 kV/μs
CI Input capacitance VI = VCC/2 + 0.4 × sin (2πft), f = 1 MHz, VCC = 5 V 2 pF
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.10 Supply Current Characteristics–5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current Disable EN1 = EN2 = 0V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.7 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.3 4.6 mA
10 Mbps ICC1, ICC2 4.2 5.6 mA
100 Mbps ICC1, ICC2 13.7 16.6 mA
ISO7842DWW AND ISO7842FDWW
Supply current Disable EN1 = EN2 = 0V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.8 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.4 4.7 mA
10 Mbps ICC1, ICC2 4.3 5.9 mA
100 Mbps ICC1, ICC2 14 17.3 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.11 Electrical Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA; see Figure 11 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 2 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V, VCM = 1500 V; see Figure 14 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.12 Supply Current Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.7 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.3 4.5 mA
10 Mbps ICC1, ICC2 4 5.2 mA
100 Mbps ICC1, ICC2 10.8 12.9 mA
ISO7842DWW and ISO7842FDWW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.8 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.4 4.7 mA
10 Mbps ICC1, ICC2 4.1 5.5 mA
100 Mbps ICC1, ICC2 11 13.6 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.13 Electrical Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –1 mA; see Figure 11 VCCO(1) – 0.4 VCCO(1) – 0.2 V
VOL Low-level output voltage IOL = 1 mA; see Figure 11 0.2 0.4 V
VI(HYS) Input threshold voltage hysteresis 0.1 × VCCI(1) V
IIH High-level input current VIH = VCCI(1) at INx or ENx 10 μA
IIL Low-level input current VIL = 0 V at INx or ENx –10 μA
CMTI Common-mode transient immunity VI = VCCI(1) or 0 V, VCM = 1500 V; see Figure 14 100 kV/μs
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.14 Supply Current Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS SUPPLY CURRENT MIN TYP MAX UNIT
ISO7842DW AND ISO7842FDW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.7 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.1 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.2 4.5 mA
10 Mbps ICC1, ICC2 3.7 5.1 mA
100 Mbps ICC1, ICC2 8.9 10.8 mA
ISO7842DWW AND ISO7842FDWW
Supply current Disable EN1 = EN2 = 0 V, VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 1 1.5 mA
EN1 = EN2 = 0 V, VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 3.4 4.8 mA
DC signal VI = 0 V (ISO7842F), VI = VCCI(1) (ISO7842) ICC1, ICC2 2 2.8 mA
VI = VCCI(1) (ISO7842F), VI = 0 V (ISO7842) ICC1, ICC2 4.4 6.3 mA
All channels switching with square wave clock input;
CL = 15 pF		 1 Mbps ICC1, ICC2 3.3 4.6 mA
10 Mbps ICC1, ICC2 3.8 5.3 mA
100 Mbps ICC1, ICC2 9 11.5 mA
(1) VCCI = Input-side VCC; VCCO = Output-side VCC.

6.15 Switching Characteristics—5-V Supply

VCC1 = VCC2 = 5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 6 11 16 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.55 4.1 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.5 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 11 1.7 3.9 ns
tf Output signal fall time 1.9 3.9 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 12 20 ns
tPLZ Disable propagation delay, low-to-high impedance output 12 20 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7842 10 20 ns
Enable propagation delay, high impedance-to-high output for ISO7842F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7842F 10 20 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 13 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.90 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.16 Switching Characteristics—3.3-V Supply

VCC1 = VCC2 = 3.3 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 6 10.8 16 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.7 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 11 0.8 3 ns
tf Output signal fall time 0.8 3 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 17 32 ns
tPLZ Disable propagation delay, low-to-high impedance output 17 32 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7842 17 32 ns
Enable propagation delay, high impedance-to-high output for ISO7842F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7842F 17 32 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 13 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.17 Switching Characteristics—2.5-V Supply

VCC1 = VCC2 = 2.5 V ±10% (over recommended operating conditions unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH, tPHL Propagation delay time See Figure 11 7.5 11.7 17.5 ns
PWD Pulse width distortion(1) |tPHL – tPLH| 0.66 4.2 ns
tsk(o) Channel-to-channel output skew time(2) Same-direction Channels 2.2 ns
tsk(pp) Part-to-part skew time(3) 4.5 ns
tr Output signal rise time See Figure 11 1 3.5 ns
tf Output signal fall time 1.2 3.5 ns
tPHZ Disable propagation delay, high-to-high impedance output See Figure 12 22 45 ns
tPLZ Disable propagation delay, low-to-high impedance output 22 45 ns
tPZH Enable propagation delay, high impedance-to-high output for ISO7842 18 45 ns
Enable propagation delay, high impedance-to-high output for ISO7842F 2 2.5 μs
tPZL Enable propagation delay, high impedance-to-low output for ISO7842 2 2.5 μs
Enable propagation delay, high impedance-to-low output for ISO7842F 18 45 ns
tfs Default output delay time from input power loss Measured from the time VCC goes below 1.7 V. See Figure 13 0.2 9 μs
tie Time interval error 216 – 1 PRBS data at 100 Mbps 0.91 ns
(1) Also known as pulse skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

6.18 Insulation Characteristics Curves

ISO7842 ISO7842F tddb_curve_reinforced_dw.gif
TA upto 150°C Operating lifetime = 135 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 1500 VRMS
Figure 1. Reinforced Isolation Capacitor Life Time Projection for Devices in DW Package
ISO7842 ISO7842F tddb_curve_reinforced_dww.gif
TA upto 150°C Operating lifetime = 34 years
Stress-voltage frequency = 60 Hz
Isolation working voltage = 2000 VRMS
Figure 2. Reinforced Isolation Capacitor Life Time Projection for Devices in DWW Package
ISO7842 ISO7842F D014_SLLSEJ0.gif Figure 3. Thermal Derating Curve for Limiting Current per VDE
ISO7842 ISO7842F D015_SLLSEJ0.gif Figure 4. Thermal Derating Curve for Limiting Power per VDE

6.19 Typical Characteristics

ISO7842 ISO7842F D001_SLLSEJ0.gif
TA = 25°C CL = 15 pF
Figure 5. Supply Current vs Data Rate (With 15-pF Load)
ISO7842 ISO7842F D003_SLLSEJ0.gif
TA = 25°C
Figure 7. High-Level Output Voltage vs High-level Output Current
ISO7842 ISO7842F D005_SLLSEJ0.gif
Figure 9. Power Supply Undervoltage Threshold vs Free-Air Temperature
ISO7842 ISO7842F D002_SLLSEJ0.gif
TA = 25°C CL = No Load
Figure 6. Supply Current vs Data Rate (With No Load)
ISO7842 ISO7842F D004_SLLSEJ0.gif
TA = 25°C
Figure 8. Low-Level Output Voltage vs Low-Level Output Current
ISO7842 ISO7842F D006_SLLSEJ0.gif
Figure 10. Propagation Delay Time vs Free-Air Temperature

7 Parameter Measurement Information

ISO7842 ISO7842F switch_test_circuit_sllsek9.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 11. Switching Characteristics Test Circuit and Voltage Waveforms
ISO7842 ISO7842F delay_tim_llsek9.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 12. Enable/Disable Propagation Delay Time Test Circuit and Waveform
ISO7842 ISO7842F failsafe_LLSE83.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. Default Output Delay Time Test Circuit and Voltage Waveforms
ISO7842 ISO7842F com_tran_imm_test_circ_sllsek9.gif
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 14. Common-Mode Transient Immunity Test Circuit

 
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