LMX1205_CASCADED_REF_BOARD

The LMX1205 Multisite evaluation module (EVM) is designed to evaluate the cascaded clock tree performance of the LMX1205, which is a four-output, ultra-low additive jitter radio-frequency (RF) buffer, divider and multiplier. Each IC in this EVM can buffer RF clocking input up to 12.8GHz; multiply input by up to eight in the output range of 6.4GHz to 12.8GHz; and divide inputs by up to eight. Each clock path has a programmable input and output delay option with a resolution of ~1ps and total range of over 50ps. This allows user to adjust clock to clock skew, cable and trace lenght mismatch and correct for any setup imperfections
A separate auxiliary clock divider is included for field-programmable gate arrays (FPGAs) and logic clocking, and each output includes a system reference (SYSREF) complement with picosecond precision and delay tuning capability. Multiple devices can be synchronized for wide clock distribution trees. The EVM has a primary device which then drive 2 secondary devices and provides user a platform to evaluate all the features essential in a cascaded clock tree phased array system.

特性

射频 PLL 和合成器