This reference design generates a 3.3V/12A output from a wide 18V-60V telecom input. The UCC2897A controls an active clamp forward converter power stage. The low gate charge and low RDSon of the CSD17501Q5A and CSD18502Q5B, implemented as self-driven synchronous rectifiers, provide for an efficient design. This design is laid out in a standard quarter brick footprint and includes enable, positive rail remote sense, and output trimming features.
| Output voltage options | PMP8790.1 |
|---|---|
| Vin (Min) (V) | 18 |
| Vin (Max) (V) | 60 |
| Vout (Nom) (V) | 3.3 |
| Iout (Max) (A) | 12 |
| Output Power (W) | 39.6 |
| Isolated/Non-Isolated | Isolated |
| Input Type | DC |
| Topology | Forward- Active Clamp^Forward- Synchronous |
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Download ready-to-use system files to speed your design process.
Test results for the reference design, including efficiency graphs, test prerequisites and more
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Detailed schematic diagram for design layout and components
Includes TI products in the design and potential alternatives.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Test report | PMP8790 Test Results | Feb 25, 2013 |
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