| Class |
Document |
Source |
Message |
Time |
Date |
No. |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (35.116mil < 75mil) Between Area Fill (1264mil,433mil) (1304mil,453mil) on Layer 5 - GND And Pad J23-MH4(1237.557mil,355mil) on Multi-Layer |
12:13:47 PM |
1/2/2019 |
1 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (40.361mil < 75mil) Between Area Fill (434mil,2404mil) (453mil,2446mil) on Layer 5 - GND And Pad J34-MH4(354.134mil,2482mil) on Multi-Layer |
12:13:47 PM |
1/2/2019 |
2 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (34.614mil < 75mil) Between Area Fill (4259mil,434mil) (4299mil,454mil) on Layer 5 - GND And Pad J26-MH4(4237.557mil,355mil) on Multi-Layer |
12:13:47 PM |
1/2/2019 |
3 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (35.193mil < 75mil) Between Area Fill (3267mil,432mil) (3307mil,452mil) on Layer 5 - GND And Pad J25-MH4(3237.558mil,355mil) on Multi-Layer |
12:13:47 PM |
1/2/2019 |
4 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (36.064mil < 75mil) Between Area Fill (2264mil,434mil) (2304mil,454mil) on Layer 5 - GND And Pad J24-MH4(2237.557mil,355mil) on Multi-Layer |
12:13:47 PM |
1/2/2019 |
5 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (38.083mil < 75mil) Between Area Fill (2264mil,434mil) (2304mil,454mil) on Layer 5 - GND And Via (2338mil,488mil) from Layer 1 - Top Layer to Layer 6 - Bottom Layer |
12:13:47 PM |
1/2/2019 |
6 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (37.508mil < 75mil) Between Area Fill (3267mil,432mil) (3307mil,452mil) on Layer 5 - GND And Via (3338mil,488mil) from Layer 1 - Top Layer to Layer 6 - Bottom Layer |
12:13:47 PM |
1/2/2019 |
7 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (40.931mil < 75mil) Between Area Fill (4259mil,434mil) (4299mil,454mil) on Layer 5 - GND And Via (4336mil,489mil) from Layer 1 - Top Layer to Layer 6 - Bottom Layer |
12:13:47 PM |
1/2/2019 |
8 |
| [Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Clearance Constraint: (38.837mil < 75mil) Between Area Fill (1264mil,433mil) (1304mil,453mil) on Layer 5 - GND And Via (1337mil,489mil) from Layer 1 - Top Layer to Layer 6 - Bottom Layer |
12:13:47 PM |
1/2/2019 |
9 |
| [Component Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Component Clearance Constraint: (Collision < 10mil) Between LCC Component U10-LM5141QRGERQ1 (3491.378mil,5816.378mil) on Layer 1 - Top Layer And SMT Small Component NT1-Net-Tie (3481.378mil,5756.378mil) on Layer 1 - Top Layer |
12:13:47 PM |
1/2/2019 |
10 |
| [Component Clearance Constraint Violation] |
PCB1_test.PcbDoc |
Advanced PCB |
Component Clearance Constraint: (Collision < 10mil) Between SMT Small Component NT2-Net-Tie (3313.842mil,4730.858mil) on Layer 6 - Bottom Layer And Component U8-LM5121MH/NOPB (3399.842mil,4803.858mil) on Layer 6 - Bottom Layer |
12:13:47 PM |
1/2/2019 |
11 |
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