| Environment Settings | ||||
| Environment Variable | xst | ngdbuild | map | par |
| LD_LIBRARY_PATH | /home/cadtools/xilinx.ISE/12.2/ISE//lib/lin64: /cadtools/openSource.qt/4.4.3/lib |
/home/cadtools/xilinx.ISE/12.2/ISE//lib/lin64: /cadtools/openSource.qt/4.4.3/lib |
/home/cadtools/xilinx.ISE/12.2/ISE//lib/lin64: /cadtools/openSource.qt/4.4.3/lib |
/home/cadtools/xilinx.ISE/12.2/ISE//lib/lin64: /cadtools/openSource.qt/4.4.3/lib |
| PATH | /home/cadtools/xilinx.ISE/12.2/ISE//bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/ISE/bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/PlanAhead/bin: /cadtools/nsc.adp/R3.1/projenv: /cadtools/nsc.adp/R3.1/ADP/cadtools/nsc.adp/bin: /cadtools/openSource.qt/4.4.3/bin: /cadtools/openSource.python/2.5.1/bin: .: /usr/bin: /usr/X11R6/bin: /usr/local/bin: /bin: /cadtools/nsc.wrappers/bin/: /home/ID_tools/WRAPPERS_ID/v1.0/bin |
/home/cadtools/xilinx.ISE/12.2/ISE//bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/ISE/bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/PlanAhead/bin: /cadtools/nsc.adp/R3.1/projenv: /cadtools/nsc.adp/R3.1/ADP/cadtools/nsc.adp/bin: /cadtools/openSource.qt/4.4.3/bin: /cadtools/openSource.python/2.5.1/bin: .: /usr/bin: /usr/X11R6/bin: /usr/local/bin: /bin: /cadtools/nsc.wrappers/bin/: /home/ID_tools/WRAPPERS_ID/v1.0/bin |
/home/cadtools/xilinx.ISE/12.2/ISE//bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/ISE/bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/PlanAhead/bin: /cadtools/nsc.adp/R3.1/projenv: /cadtools/nsc.adp/R3.1/ADP/cadtools/nsc.adp/bin: /cadtools/openSource.qt/4.4.3/bin: /cadtools/openSource.python/2.5.1/bin: .: /usr/bin: /usr/X11R6/bin: /usr/local/bin: /bin: /cadtools/nsc.wrappers/bin/: /home/ID_tools/WRAPPERS_ID/v1.0/bin |
/home/cadtools/xilinx.ISE/12.2/ISE//bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/ISE/bin/lin64: /home/cadtools-dev/xilinx.ISE/12.2/PlanAhead/bin: /cadtools/nsc.adp/R3.1/projenv: /cadtools/nsc.adp/R3.1/ADP/cadtools/nsc.adp/bin: /cadtools/openSource.qt/4.4.3/bin: /cadtools/openSource.python/2.5.1/bin: .: /usr/bin: /usr/X11R6/bin: /usr/local/bin: /bin: /cadtools/nsc.wrappers/bin/: /home/ID_tools/WRAPPERS_ID/v1.0/bin |
| XILINX | /home/cadtools/xilinx.ISE/12.2/ISE/ | /home/cadtools/xilinx.ISE/12.2/ISE/ | /home/cadtools/xilinx.ISE/12.2/ISE/ | /home/cadtools/xilinx.ISE/12.2/ISE/ |
| XILINXD_LICENSE_FILE | 27003@sky | 27003@sky | 27003@sky | 27003@sky |
| XIL_PAR_ALLOW_LVDS_LOC_OVERRIDE | < set > | < set > | < set > | < set > |
| Synthesis Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ifn | adc08d1520.prj | ||
| -ifmt | mixed | MIXED | |
| -ofn | adc08d1520 | ||
| -ofmt | NGC | NGC | |
| -p | xc4vlx25-11-ff668 | ||
| -top | adc08d1520 | ||
| -opt_mode | Optimization Goal | Speed | Speed |
| -opt_level | Optimization Effort | 1 | 1 |
| -power | Power Reduction | NO | NO |
| -iuc | Use synthesis Constraints File | NO | NO |
| -keep_hierarchy | Keep Hierarchy | No | NO |
| -netlist_hierarchy | Netlist Hierarchy | As_Optimized | As_Optimized |
| -rtlview | Generate RTL Schematic | Yes | NO |
| -glob_opt | Global Optimization Goal | AllClockNets | AllClockNets |
| -read_cores | Read Cores | YES | YES |
| -sd | Cores Search Directories | {"../coregen" } | |
| -write_timing_constraints | Write Timing Constraints | NO | NO |
| -cross_clock_analysis | Cross Clock Analysis | NO | NO |
| -bus_delimiter | Bus Delimiter | <> | <> |
| -slice_utilization_ratio | Slice Utilization Ratio | 100 | 100% |
| -bram_utilization_ratio | BRAM Utilization Ratio | 100 | 100% |
| -dsp_utilization_ratio | DSP Utilization Ratio | 100 | 100% |
| -verilog2001 | Verilog 2001 | YES | YES |
| -fsm_extract | YES | YES | |
| -fsm_encoding | Auto | AUTO | |
| -safe_implementation | No | NO | |
| -fsm_style | LUT | LUT | |
| -ram_extract | Yes | YES | |
| -ram_style | Auto | AUTO | |
| -rom_extract | Yes | YES | |
| -shreg_extract | YES | YES | |
| -rom_style | Auto | AUTO | |
| -auto_bram_packing | NO | NO | |
| -resource_sharing | YES | YES | |
| -async_to_sync | NO | NO | |
| -use_dsp48 | Auto | AUTO | |
| -iobuf | YES | YES | |
| -max_fanout | 500 | 500 | |
| -bufg | 32 | 32 | |
| -register_duplication | YES | YES | |
| -register_balancing | No | NO | |
| -optimize_primitives | NO | NO | |
| -use_clock_enable | Auto | AUTO | |
| -use_sync_set | Auto | AUTO | |
| -use_sync_reset | Auto | AUTO | |
| -iob | Auto | AUTO | |
| -equivalent_register_removal | YES | YES | |
| -slice_utilization_ratio_maxmargin | 5 | 0% | |
| Translation Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -intstyle | ise | None | |
| -dd | _ngo | None | |
| -p | xc4vlx25-ff668-11 | None | |
| -sd | Macro Search Path | ../coregen | None |
| -uc | /home/scusers/csipsc/ADC08D1520/ucf/adc08d1520.ucf | None | |
| Map Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -ir | Use RLOC Constraints | OFF | OFF |
| -cm | Optimization Strategy (Cover Mode) | area | area |
| -intstyle | ise | None | |
| -o | adc08d1520_map.ncd | None | |
| -pr | Pack I/O Registers/Latches into IOBs | off | off |
| -p | xc4vlx25-ff668-11 | None | |
| Place and Route Property Settings | |||
| Switch Name | Property Name | Value | Default Value |
| -t | 1 | 1 | |
| -intstyle | ise | ||
| -ol | Place & Route Effort Level (Overall) | high | std |
| -w | true | false | |
| Operating System Information | ||||
| Operating System Information | xst | ngdbuild | map | par |
| CPU Architecture/Speed | Intel(R) Xeon(R) CPU W3530 @ 2.80GHz/2800.253 MHz | Intel(R) Xeon(R) CPU W3530 @ 2.80GHz/2800.253 MHz | Intel(R) Xeon(R) CPU W3530 @ 2.80GHz/2800.253 MHz | Intel(R) Xeon(R) CPU W3530 @ 2.80GHz/2800.253 MHz |
| Host | zaire | zaire | zaire | zaire |
| OS Name | RedHatDesktop | RedHatDesktop | RedHatDesktop | RedHatDesktop |
| OS Release | Red Hat Desktop release 4 (Nahant Update 8) | Red Hat Desktop release 4 (Nahant Update 8) | Red Hat Desktop release 4 (Nahant Update 8) | Red Hat Desktop release 4 (Nahant Update 8) |