The TMP110 is a I2C-compatible digital temperature sensor in an ultra-small (0.64mm2) 5-pin package. The small size and height package optimizes volume constrained systems where DSBGA packages can be considered unsuitable. Unlike DSBGA packages of comparable size, TMP110 provides a 5th pin that can either be used as an address pin or alert pin, providing flexibility for both scalability of number of sensors or monitoring critical thermal events.
The TMP110 offers an accuracy of ±1.0°C across the temperature range with an on-chip 12-bit analog-to-digital converter (ADC) that provides a temperature resolution of 0.0625°C.
The TMP110 is designed to operate from a supply range as low as 1.14V, with a low average and shutdown current of 3.2µA (at 1Hz) and 0.15µA, respectively, allowing for an on-demand temperature conversion and maximizing of battery life. The supply can also be raised to as high as 5.5V for a range of industrial applications.
Pin-to-pin and software compatible options are available.
| DEVICE | BEST ACCURACY (MAXIMUM) | SOFTWARE COMPATIBLE | ADDRESS/ALERT PIN FUNCTIONALITY | PACKAGE OPTIONS | 
|---|---|---|---|---|
| TMP102 | 2.0 °C | Yes | Address + Alert | DRL (6-pin SOT563) (1.6mm × 1.6mm) | 
| TMP110 | 1.0 °C | Yes | Separate (Address & Alert) | DPW (5-pin X2SON) (0.8mm × 0.8mm) | 
| TMP112 | 0.5 °C | Yes | Address + Alert (DRL) | DRL (6-pin SOT563) (1.6mm × 1.6mm) | 
| Separate (Address & Alert) (DPW) | DPW (5-pin X2SON) (0.8mm × 0.8mm) | 
| PIN | TYPE(1) | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | NO. | ||
| GND | 1 | 1 | — | Ground Pin-1 has curved edges. | 
| SCL | 2 | 2 | I | Serial clock | 
| ADD0 (TMP110D) | 3 | — | I | Address select. Connect to GND, SCL, SDA or V+. Only for Address variant. | 
| ALERT (TMP110D0, TMP110D1, | — | 3 | O | Overtemperature alert(2). Open-drain output; requires a pullup resistor. Only for Alert variant. Note: Connecting to GND if Alert pin is not used is preferred. | 
| SDA | 4 | 4 | I/O | Serial data input. Open-drain output; requires a pullup resistor. | 
| V+ | 5 | 5 | I | Supply voltage | 
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Supply voltage | V+ | –0.3 | 6 | V | 
| Input/Output voltage | SCL, SDA, ADD0, ALERT | –0.3 | 6 | V | 
| Output current | ±10 | mA | ||
| Operating temperature, TA | –40 | 125 | °C | |
| Junction temperature, TJ | 150 | °C | ||
| Storage temperature, Tstg | –55 | 150 | °C | |
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | 
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| V+ | Supply voltage | 1.14 | 3.3 | 5.5 | V | 
| VI/O | SCL, SDA, ADD0, ALERT | 0 | 5.5 | V | |
| IOL | SDA, ALERT | 0 | 3 | mA | |
| TA | Operating ambient temperature | -40 | 125 | °C | |
| THERMAL METRIC(1) | TMP110 | UNIT | |
|---|---|---|---|
| DPW | |||
| 5-pins | |||
| RθJA | Junction-to-ambient thermal resistance | 230 | °C/W | 
| RθJC(top) | Junction-to-case (top) thermal resistance | 194 | °C/W | 
| RθJB | Junction-to-board thermal resistance | 158.4 | °C/W | 
| ΨJT | Junction-to-top characterization parameter | 20 | °C/W | 
| ΨJB | Junction-to-board characterization parameter | 158.3 | °C/W | 
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 108.4 | °C/W | 
| MT | Thermal Mass | 0.46 | mJ/°C | 
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| TEMPERATURE SENSOR | |||||||
| TERR | Accuracy (temperature error) | -40°C to 125°C | 1.14V ≤ V+ ≤ 1.4V | ± 2.0 | °C | ||
| 1.4V < V+ ≤ 5.5V | ± 1.0 | °C | |||||
| PSR | DC power supply rejection | V+ ≥ 1.4V | 0.02 | °C/V | |||
| TRES | Temperature resolution | 12 | Bits | ||||
| 62.5 | m°C | ||||||
| TREPEAT | Repeatability(1) | V+ = 3.3V 3 sigma distribution | ±1 | LSB | |||
| TLTD | Long-term stability and drift | 1000 hours at 125°C(2) | ±1 | LSB | |||
| tRESP_L | Response time (Stirred Liquid) | 2-layer FR4 PCB 1.5748 mm thickness | τ = 63% for step response from 25°C to 75°C | 1.45 | s | ||
| THYST | Temperature cycling and hysteresis(3) | 0.0625 | °C | ||||
| tACT | Active conversion time | V+ ≥ 1.4V | 10.25 | 11.25 | ms | ||
| V+ < 1.4V | 10.5 | 12 | |||||
| tVAR | Timing variation of all device settings | V+ ≥ 1.4V | -10 | 10 | % | ||
| V+ < 1.4V | -15 | 15 | |||||
| DIGITAL INPUT/OUTPUT | |||||||
| CIN | Input capacitance | 3 | pF | ||||
| VIH | Input logic high | V+ < 1.4V | 0.8 × V+ | V | |||
| 1.4V ≤ V+ | 0.7 × V+ | V | |||||
| VIL | Input logic low | V+ < 1.4V | -0.3 | 0.2 × V+ | V | ||
| 1.4V ≤ V+ | -0.3 | 0.3 × V+ | V | ||||
| VHYST | Hysteresis | 0.1 | V | ||||
| IIN | Input current | ± 0.1 | μA | ||||
| VOL | Output logic | V+ ≥ 1.4V | IOL = –3mA | 0.13 | 0.4 | V | |
| V+ < 1.4V | IOL = –0.75mA | 0.2 | V | ||||
| POWER SUPPLY | |||||||
| IDD_ACTIVE | Supply current during active conversion | Active Conversion, serial bus idle | 55 | 90 | μA | ||
| IDD_AVG | Average current consumption | Continous conversion mode 1Hz conversion period | Serial bus idle | 3.2 | μA | ||
| SCL = 1MHz | 13.5 | ||||||
| IDD_SB | Standby current(4) | Continous conversion mode Serial bus idle | 2.6 | 5 | μA | ||
| IDD_SD | Shutdown current | TA = +25°C, Serial bus inactive | 0.15 | 0.35 | μA | ||
| TA = -40°C to 125°C | 1.5 | ||||||
| Serial bus active, SCL frequency = 400kHz | 5.5 | ||||||
| Serial bus active, SCL frequency = 1MHz | 13 | ||||||
| VPOR | Power-on reset threshold voltage | Supply rising | 1.02 | 1.06 | V | ||
| Brownout detect | Supply falling | 0.94 | 0.97 | V | |||
| tINIT | Power-on reset time | 0.5 | ms | ||||
| tRESET | Reset Time | General Call Reset | 0.1 | ms | |||
| FAST MODE | FAST MODE PLUS | UNIT | |||||
|---|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | ||||
| f(SCL) | SCL operating frequency | 1 | 400 | 1 | 1000 | kHz | |
| t(BUF) | Bus-free time between STOP and START conditions | 0.6 | 0.5 | µs | |||
| t(SUSTA) | Repeated START condition setup time | 0.6 | 0.26 | µs | |||
| t(HDSTA) | Hold time after repeated START condition. After this period, the first clock is generated. | 0.6 | 0.26 | µs | |||
| t(SUSTO) | STOP condition setup time | 0.6 | 0.26 | µs | |||
| t(HDDAT) | Data hold time(2) | 100 | 900 | 12 | 150 | ns | |
| t(SUDAT) | Data setup time | 100 | 50 | ns | |||
| t(LOW) | SCL clock low period | 1.3 | 0.5 | µs | |||
| t(HIGH) | SCL clock high period | 0.6 | 0.26 | µs | |||
| t(VDAT) | Data valid time (data response time)(3) | 0.9 | 0.45 | µs | |||
| tR | SDA, SCL rise time | 300 | 120 | ns | |||
| tF | SDA, SCL fall time | 300 | 20 x (V+ / 5.5V) | 120 | ns | ||
| ttimeout | Timeout (SCL = GND or SDA = GND) | 30 | 30 | ms | |||
| tLPF | Glitch suppression filter | 50 | 50 | ns | |||