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IWR6843AOP Single-Chip 60 to 64GHz mmWave Sensor Antennas-On-Package (AOP)
SWRS237C
April 2020 – June 2025
IWR6843AOP
PRODUCTION DATA
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IWR6843AOP Single-Chip 60 to 64GHz mmWave Sensor Antennas-On-Package (AOP)
1
1
Features
2
Applications
3
Description
4
Functional Block Diagram
5
Device Comparison
5.1
Related Products
6
Terminal Configuration and Functions
6.1
Pin Diagram
6.2
Signal Descriptions
6.2.1
Pin Functions - Digital and Analog [ALP Package]
6.3
Pin Attributes
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Power-On Hours (POH)
7.4
Recommended Operating Conditions
7.5
VPP Specifications for One-Time Programmable (OTP) eFuses
7.5.1
Recommended Operating Conditions for OTP eFuse Programming
7.5.2
Hardware Requirements
7.5.3
Impact to Your Hardware Warranty
7.6
Power Supply Specifications
7.7
Power Consumption Summary
7.8
Power Save Mode
7.9
RF Specification
7.10
CPU Specifications
7.11
Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
7.12
Timing and Switching Characteristics
7.12.1
Antenna Radiation Patterns
7.12.1.1
Antenna Radiation Patterns for Receiver
7.12.1.2
Antenna Radiation Patterns for Transmitter
7.12.2
Antenna Positions
7.12.3
Power Supply Sequencing and Reset Timing
7.12.4
Input Clocks and Oscillators
7.12.4.1
Clock Specifications
7.12.5
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
7.12.5.1
Peripheral Description
7.12.5.2
MibSPI Transmit and Receive RAM Organization
7.12.5.2.1
SPI Timing Conditions
7.12.5.2.2
SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
7.12.5.2.3
SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
7.12.5.3
SPI Peripheral Mode I/O Timings
7.12.5.3.1
SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
7.12.5.4
Typical Interface Protocol Diagram (Peripheral Mode)
7.12.6
LVDS Interface Configuration
7.12.6.1
LVDS Interface Timings
7.12.7
General-Purpose Input/Output
7.12.7.1
Switching Characteristics for Output Timing versus Load Capacitance (CL)
7.12.8
Controller Area Network - Flexible Data-rate (CAN-FD)
7.12.8.1
Dynamic Characteristics for the CANx TX and RX Pins
7.12.9
Serial Communication Interface (SCI)
7.12.9.1
SCI Timing Requirements
7.12.10
Inter-Integrated Circuit Interface (I2C)
7.12.10.1
I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
7.12.11
Quad Serial Peripheral Interface (QSPI)
7.12.11.1
QSPI Timing Conditions
7.12.11.2
Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
7.12.11.3
QSPI Switching Characteristics
7.12.12
ETM Trace Interface
7.12.12.1
ETMTRACE Timing Conditions
7.12.12.2
ETM TRACE Switching Characteristics
7.12.13
Data Modification Module (DMM)
7.12.13.1
DMM Timing Requirements
7.12.14
JTAG Interface
7.12.14.1
JTAG Timing Conditions
7.12.14.2
Timing Requirements for IEEE 1149.1 JTAG
7.12.14.3
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Subsystems
8.3.1
RF and Analog Subsystem
8.3.1.1
Clock Subsystem
8.3.1.2
Transmit Subsystem
8.3.1.3
Receive Subsystem
8.3.2
Processor Subsystem
8.3.3
Host Interface
8.3.4
Main Subsystem Cortex-R4F
8.3.5
DSP Subsystem
8.3.6
Hardware Accelerator
8.4
Other Subsystems
8.4.1
ADC Channels (Service) for User Application
8.4.1.1
GP-ADC Parameter
8.5
Boot Modes
8.5.1
Flashing Mode
8.5.2
Functional Mode
9
Monitoring and Diagnostics
9.1
Monitoring and Diagnostic Mechanisms
9.1.1
Error Signaling Module
10
Applications, Implementation, and Layout
10.1
Application Information
10.2
Reference Schematic
11
Device and Documentation Support
11.1
Device Nomenclature
11.2
Tools and Software
11.3
Documentation Support
11.4
Support Resources
11.5
Trademarks
11.6
Electrostatic Discharge Caution
11.7
Glossary
12
Revision History
13
Mechanical, Packaging, and Orderable Information
13.1
Tray Information for ALP, 15 × 15 mm
IMPORTANT NOTICE
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Data Sheet
IWR6843AOP Single-Chip 60 to 64GHz mmWave Sensor
Antennas-On-Package (AOP)
1
Features
FMCW transceiver
Integrated 4 receivers and 3 transmitters Antennas-On-Package (AOP)
Integrated PLL, transmitter, receiver, Baseband, and ADC
60 to 64GHz coverage with 4GHz continuous bandwidth
Supports 6-bit phase shifter for TX Beam forming
Ultra-accurate chirp engine based on fractional-N PLL
Built-in calibration and self-test
Arm®
Cortex®
-R4F-based radio control system
Built-in firmware (ROM)
Self-calibrating system across process and temperature
Embedded self-monitoring with no host processor involvement on Functional Safety-Compliant devices
C674x DSP for advanced signal processing
Memory compression
Hardware accelerator for FFT, filtering, and CFAR processing
Arm-R4F microcontroller for object detection, and interface control
Supports autonomous mode (loading user application from QSPI flash memory)
Internal memory with ECC
1.75MB, divided into MSS program RAM (512KB), MSS data RAM (192KB), DSP L1 RAM (64KB) and L2 RAM (256KB), and L3 radar data cube RAM (768KB)
Technical reference manual includes allowed size modifications
Device Security (
on select part numbers
)
Secure authenticated and encrypted boot support
Customer programmable root keys, symmetric keys (256 bit), Asymmetric keys (up to RSA-2K) with Key revocation capability
Crypto software accelerators - PKA , AES (up to 256 bit), SHA (up to 256 bit), TRNG/DRGB
Other interfaces available to user application
Up to 6 ADC channels (low sample rate monitoring)
Up to 2 SPI ports
Up to 2 UARTs
1 CAN-FD interface
I2C
GPIOs
2 lane LVDS interface for raw ADC data and debug instrumentation
Functional Safety-Compliant
Developed for functional safety applications
Documentation available to aid IEC 61508 functional safety system design up to SIL 3
Hardware integrity up to SIL-2
Safety-related certification
IEC 61508 certified upto SIL 2 by TUV SUD
Power management
Built-in LDO network for enhanced PSRR
I/Os support dual voltage 3.3V/1.8V
Clock source
40.0MHz crystal with internal oscillator
Supports external oscillator at 40MHz
Supports externally driven clock (square/sine) at 40MHz
Easy hardware design
0.8mm pitch, 180-pin 15mm × 15mm FCBGA package (ALP) for easy assembly and low-cost PCB design
Small solution size
Operating conditions
Junction temp range: –40°C to 105°C