AM62Lx Sitara™ Processors Silicon Errata, Silicon Revision 1.0, 1.1

1 Usage Notes and Advisories Matrices

Table 1-1 lists all usage notes and the applicable silicon revision(s). Table 1-2 lists all advisories, modules affected, and the applicable silicon revision(s).

Table 1-1 Usage Notes Matrix

MODULE	DESCRIPTION	SILICON REVISIONS AFFECTED
MODULE	DESCRIPTION	AM62Lx 1.0	AM62Lx 1.1
DDR	i2330 DDRSS Register Configuration Tool Updates	YES	YES
OSPI	i2351 OSPI: Direct Access Controller (DAC) does not support Continuous Read mode with NAND Flash	YES	YES

Table 1-2 Advisories Matrix

MODULE	DESCRIPTION	SILICON REVISIONS AFFECTED
MODULE	DESCRIPTION	AM62Lx 1.0	AM62Lx 1.1
BCDMA	i2431 BCDMA: RX Channel can lockup in certain scenarios	YES	YES
Boot	i2435 Boot: ROM timeout for eMMC boot too long	YES	NO⁽¹⁾
Boot	i2462 Boot: ROM xSPI-SFDP boot mode fails	YES	NO⁽¹⁾
Boot	i2463 Boot: Possible boot failure with SD cards	YES	NO⁽¹⁾
Boot	i2464 Boot: ROM is unable to boot from SD cards with incorrect formatting	YES	YES
Boot	i2465 Boot: EMMC boot mode is slower than expected	YES	NO⁽¹⁾
Boot	i2466 Boot: ROM boot fails for large file sizes	YES	YES
Boot	i2467 Boot: ROM UART boot fails with large image	YES	NO⁽¹⁾
Boot	i2469 Boot: ROM NOBOOT boot mode is not functional	YES	YES
Boot	i2470 Boot: USB-DFU primary boot mode fails to transition to backup boot mode	YES	NO⁽¹⁾
Boot	i2471 Boot: Certain primary/backup boot mode combinations fail	YES	NO⁽¹⁾
Boot	i2473 Boot: eMMC boot may fail	YES	NO⁽¹⁾
Boot	i2474 Boot: Certain second stage binaries fail for block based boot modes	YES	NO⁽¹⁾
Boot	i2481 Boot: eMMC alternate boot fails if partition is not reprogrammed every time	YES	NO⁽¹⁾
Boot	i2482 Boot: ROM does not provide enough clocks during SD card initialization	YES	NO⁽¹⁾
Boot	i2484 Boot: ROM fails to parse X509 certificates using GENERALIZED time format	YES	NO⁽¹⁾
CPSW	i2208 CPSW: ALE IET Express Packet Drops	YES	YES
CPSW	i2401 CPSW: Host Timestamps Cause CPSW Port to Lock up	YES	YES
DDR	i2160 DDR: Valid VRef Range Must be Defined During LPDDR4 Command Bus Training	YES	YES
Debug	i2461 Debug: Wait-In-Reset (WIR) mode is not functional	YES	NO⁽¹⁾
LPM	i2487 LPM: Low power modes may inadvertently corrupt DDR contents	YES	NO⁽¹⁾
MCAN	i2278 MCAN: Message Transmit order not guaranteed from dedicated Tx Buffers configured with same Message ID	YES	YES
MCAN	i2279 MCAN: Specification Update for dedicated Tx Buffers and Tx Queues configured with same Message ID	YES	YES
MMCHS	i2312 MMCSD: HS200 and SDR104 Command Timeout Window Too Small	YES	YES
OSPI	i2189 OSPI: Controller PHY Tuning Algorithm	YES	YES
OSPI	i2249 OSPI: Internal PHY Loopback and Internal Pad Loopback clocking modes with DDR timing inoperable	YES	YES
OSPI	i2383 OSPI: 2-byte address is not supported in PHY DDR mode	YES	YES
PRG	i2253 PRG: CTRL_MMR STAT registers are unreliable indicators of POK threshold failure	YES	YES
USART	i2310 USART: Erroneous clear/trigger of timeout interrupt	YES	YES
USART	i2311 USART Spurious DMA Interrupts	YES	YES
USB	i2409 USB: USB2 PHY locks up due to short suspend	YES	YES

(1) This advisory is planned to be fixed in Silicon Revision 1.1. Validation of the fix is pending.

1.1 Devices Supported

This document supports the following devices:

AM62Lx

Reference documents for the supported devices are:

AM62Lx Processors Technical Reference Manual (SPRUJB4)
AM62Lx Processors Data Sheet (SPRSPA1)