SPRADG5 January   2024 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , DRA821U , DRA821U-Q1 , DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1UART Introduction
    1. 1.1 Jacinto 7 UART Overview
    2. 1.2 Jacinto 7 UART Features
    3. 1.3 Jacinto 7 UART Functional Introduction
  5. 2UART Usage Overview
    1. 2.1 WKUP_UART0 Usage
    2. 2.2 MCU_UART0 Usage
    3. 2.3 MAIN_UARTx Usage
  6. 3Log Level Design on Software Module
  7. 4Change UART Instance
    1. 4.1 Change MAIN_UARTx for MAIN Domain
    2. 4.2 Set Standalone UART Port for DSP/MCU
  8. 5Summary
  9. 6References
Application Note

UART Log Debug System on Jacinto 7 SoC