OSPI Controller PHY Tuning Algorithm
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1 Introduction
Figure 1-1 shows the OSPI controller connected to the Flash device.
The data lines (DQ[7..0]) are bidirectional. During the command and address sections of the read transaction the controller drives those pins. During the data section of the transaction the flash devices drives the data lines. Figure 1-2 is an example of 4-byte read transaction.
Figure 1-1 OSPI Controller and Flash
DeviceThe controller provides the OSPI clock to the Flash device. It is generated by delaying the ref_clk through the TX PDL. The flash device uses the clock to capture the command and address during the command and address phases. During the data phase, the OSPI device drives a new data byte on each edge of the OSPI clock. Figure 1-2 is an example of 4-byte read transaction.
Some OSPI devices provide a DQS signal. The DQS and data are edge aligned at points 4 and 5 in Figure 1-1. DQS must be delayed by the RX PDL to a point inside the data eye to sample valid data at point 2.
Figure 1-2 Timing Diagram of a Read
TransactionThe “round trip delay” of data is the time from a ref_clk edge, to the sampling time of the data triggered by that edge. The sum of delays created by the TX PDL, the travel time of the OSPI clock from the controller to the flash device, the output delay of the flash device, and the RX PDL Delay, creates the round trip delay. The controller samples the data into an RX FIFO using the Delayed DQS. The data is read by the controller out of the RX FIFO using the ref_clk.
Figure 1-3 Data SamplingThe controller expects the first byte of data to be captured within a specific ref_clk cycle (the target cycle), and all remaining data in the following cycles. In cases where the round trip delay is higher than the ref_clk period, the target cycle must be moved to the next ref_clk cycle using the Read Data Capture register’s Read Delay field OSPI_RD_DATA_CAPTURE_REG[4:1].
The goal of the tuning procedure is to select an optimal tuning point (OTP) of Read Delay, TX PDL Delay, and RX PDL Delay for sampling data.
Figure 1-4 RCLK Target Cycles1.1 Acronyms Used in This Document
| Acronym | Description |
|---|---|
| Ref_clk | The internal clock of the OSPI controller. |
| OSPI Clock | The clock of the OSPI bus. |
| DQS |
Sometimes referred to as data strobe, this is a signal provided by some OSPI devices. It acts as a high speed clock for the data lanes. The controller can use a delayed DQS to sample incoming data. |
| DLL |
Delay locked loop |
| PDL | Programmable delay line |
| OSPI PHY |
The part of the OSPI controller which sets up TX delay, and samples incoming data. |
| Read Delay |
A parameter of the OSPI controller which determines which ref_clk cycle incoming data must be sampled in. |
| Data Eye |
The period of time in which all data bits are valid. The sampling edge must occur inside the data eye for the byte to be read successfully. |
| OTP | Optimal Tuning Point |