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  • Using the Fast Serial Interface (FSI) With Multiple Devices in an Application

    • SPRACM3E August   2021  – January 2023 F29H850TU , F29H859TU-Q1 , TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280033 , TMS320F280034 , TMS320F280034-Q1 , TMS320F280036-Q1 , TMS320F280036C-Q1 , TMS320F280037 , TMS320F280037-Q1 , TMS320F280037C , TMS320F280037C-Q1 , TMS320F280038-Q1 , TMS320F280038C-Q1 , TMS320F280039 , TMS320F280039-Q1 , TMS320F280039C , TMS320F280039C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28384D , TMS320F28384S , TMS320F28386D , TMS320F28386S , TMS320F28388D , TMS320F28388S , TMS320F28P650DH , TMS320F28P650DK , TMS320F28P650SH , TMS320F28P650SK , TMS320F28P659DH-Q1 , TMS320F28P659DK-Q1 , TMS320F28P659SH-Q1

       

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  • Using the Fast Serial Interface (FSI) With Multiple Devices in an Application
  1.   Using the Fast Serial Interface (FSI) With Multiple Devices in an Application
  2.   Trademarks
  3. 1Introduction to the FSI Module
  4. 2FSI Applications
  5. 3Handshake Mechanism
    1. 3.1 Daisy-Chain Handshake Mechanism
    2. 3.2 Star Handshake Mechanism
  6. 4Sending and Receiving FSI Data Frames
    1. 4.1 FSI Data Frame Configuration APIs
    2. 4.2 Start Transmitting Data Frames
  7. 5Daisy-Chain Topology Tests
    1. 5.1 Two Device FSI Communication
      1. 5.1.1 CPU Control
      2. 5.1.2 DMA Control
      3. 5.1.3 Hardware Control
    2. 5.2 Three Device FSI Communication
      1. 5.2.1 CPU/DMA Control
      2. 5.2.2 Hardware Control
        1. 5.2.2.1 Skew Compensation for Three Device Daisy-Chain System
          1. 5.2.2.1.1 CPU/DMA control
          2. 5.2.2.1.2 Hardware Control
  8. 6Star Topology Tests
  9. 7Event Synchronization Over FSI
    1. 7.1 Introduction
      1. 7.1.1 Requirement of Event Sync for Distributed Systems
      2. 7.1.2 Solution Using FSI Event Sync Mechanism
      3. 7.1.3 Functional Overview of FSI Event Sync Mechanism
    2. 7.2 C2000Ware FSI EPWM Sync Examples
      1. 7.2.1 Location of the C2000Ware Example Project
      2. 7.2.2 Summary of Software Configurations
        1. 7.2.2.1 Lead Device Configuration
        2. 7.2.2.2 Node Device Configuration
      3. 7.2.3 1 Lead and 2 Node F28002x Device Daisy-Chain Tests
        1. 7.2.3.1 Hardware Setup and Configurations
        2. 7.2.3.2 Experimental Results
      4. 7.2.4 1 Lead and 8 Node F28002x Device Daisy-Chain Tests
        1. 7.2.4.1 Hardware Setup and Configurations
        2. 7.2.4.2 Experimental Results
      5. 7.2.5 Theoretical C2000 Uncertainties
    3. 7.3 Additional Tips and Usage of FSI Event Sync
      1. 7.3.1 Running the Example
      2. 7.3.2 Target Configuration File
      3. 7.3.3 Usage of Event Sync for Star Configuration
  10. 8References
  11. 9Revision History
  12. IMPORTANT NOTICE
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APPLICATION NOTE

Using the Fast Serial Interface (FSI) With Multiple Devices in an Application

1 Using the Fast Serial Interface (FSI) With Multiple Devices in an Application

In industrial applications, it is often necessary for multiple devices to communicate with each other in a fast, low latency, and synchronized manner. One example is in a decentralized / distributed control system architecture. A new communication peripheral created for C2000™ Real-Time Control Microcontrollers (MCU), the Fast Serial Interface (FSI) can expand its reliable high-speed communication features to multiple devices in a system. This application report demonstrates how to implement a daisy-chain or star network topology using FSI. Test results are provided to validate the high-speed communication capability of FSI with different configuration methods. You can quickly verify and design FSI in different applications using the provided source code, which can be downloaded from C2000WARE.

The target processors for the corresponding software include the TMS320F28002x, TMS320F28004x, and TMS320F2838x. The implementation methods and software can be applied and ported to future C2000 processors that include FSI. Example code discussed in this document can be found in the latest C2000WARE release, located within the following local directory after installation:

C:\ti\c2000\C2000Ware_<version_number>\driverlib\f28xxxx\examples\fsi

The available example projects are:

  • fsi_ex_daisy_handshake_lead
  • fsi_ex_daisy_handshake_node
  • fsi_ex_star_broadcast

Trademarks

C2000™ and Code Composer Studio™ are trademarks of Texas Instruments.

All trademarks are the property of their respective owners.

1 Introduction to the FSI Module

The FSI module is a serial communication peripheral capable of reliable and robust high-speed communications, up to 200 Mbps. Utilizing very few unidirectional signals, FSI provides a low cost way of communicating across an isolation barrier when leveraging digital isolation devices. Thus, FSI enables new ways of distributing the powerful sensing, processing, and actuation capabilities of C2000 MCUs in industrial applications, where real-time control with critical communication speed is required.

Generally, FSI can be implemented in two kinds of system conditions:

  • Wired communications between MCUs that exist on the same voltage and ground planes.
  • Wired communications across an isolation barrier, leveraging digital isolators (like ISO77xx), commonly used for MCUs placed on the hot-side needing to communicate with MCUs on the cold-side, or between boards with different voltage and ground planes.

There are a number of real-time systems that can benefit from the FSI peripheral. A multi-axis servo drive can be constructed with C2000 device nodes controlling each axis. Having FSI serve as the communication link, control loop information can be quickly transmitted and received between the devices to maintain precise motion control. For an example of this system see the Distributed Multi-axis Servo Drive over Fast Serial Interface (FSI) reference design.

Additionally, with increasing global power consumption, the need for higher efficiency power supplies, in conjunction with the availability of wide bandgap GaN and SiC products, is driving the use of more sophisticated power distribution architectures. Decentralized power control solutions using C2000 MCUs can be connected and made flexible with FSI to meet these requirements. For a discussion on such power related systems see the Distributed Power Control Architecture with Multiple MCUs Over FSI.

The FSI peripheral offers a broad range of features, including programmable data length, hardware managed CRC, ECC support, and more. A PING watchdog and Frame watchdog can enable automatic line-break detection. The unique delay line control feature implemented within the FSI receive module can adjust for channel-to-channel skew introduced by trace-length mismatch, transceivers, or digital isolation ICs, allowing FSI to maintain high-speed and robust communication.

The FSI consists of the independent transmitter (FSITX) and receiver (FSIRX) cores, which are configured and operated independently. Because of this, the FSI protocol does not have a notion of master and slave, unlike some other synchronous communication protocols, and allows for simultaneous full speed communications in both directions. Figure 1-1 shows the CPU interface of each FSI module. Each module owns up to three signal lines: one clock and two data signals, where the second data lines, FSITXyD1 and FSIRXyD1, are optional, and can be enabled for multi-lane transmission and double the speed for data bits. Thus, at least four signal lines are needed to create 2-way point-to-point communication. Considering the timing spec for FSITX (see the device-specific data sheets referenced in Section 8), the maximum data rate of 200 Mbps can be achieved with the maximum clock of 50 MHz, using two data lines, since the data is transmitted on both edges of the clock signal. For a full overview of FSI including all features and functions available, see the device-specific Technical Reference Manual (TRM).

GUID-43E43363-9EC2-4C63-8818-8A0EDFC9BE19-low.png Figure 1-1 FSITX and FSIRX CPU Interface

2 FSI Applications

In terms of the trend in power electronic applications, the increasing demand for higher power levels makes multiple power modules in parallel much more popular. Examples of such applications include industrial drives, telecom rectifiers, server power supplies, on-board chargers, and so forth. Meanwhile, to achieve a complex system with high performance, multiple MCUs are commonly used and must operate in a synchronized fashion. Thus, critical data, including protection signals, sampling parameters, and even control loop data, needs to be transferred with the fastest speed and least amount of latency among multiple devices/modules. FSI will be more suitable to handle this when compared to the traditional Controller Area Network (CAN), Serial Peripheral Interface (SPI) or Universal Asynchronous Receiver/Transmitter (UART).

There are a number of communication network topologies for connecting multiple devices, each with their own benefits. A ring topology can be created by connecting multiple devices with FSI communication in a daisy-chain fashion. The advantages of a ring topology are that each device only needs one FSI transmitter and receiver and also the simplicity from a physical connection perspective. Figure 2-1 shows a daisy-chain connection system for N (N≥2) node devices, where each device (index i) connects with the FSITX of device i-1 and FSIRX of device i+1.

GUID-19F81543-4921-4A00-88FA-FBF92DB1770A-low.png Figure 2-1 Daisy-Chain Connection Example

One disadvantage of the above daisy-chain topology is that if one device in the chain fails then the entire communication link is broken. Another downside is that devices must forward data along to the next device in the chain if the received data is intended for a subsequent device. This can add to the overall latency of when a data packet is transmitted and when the respective device in the chain receives the data.

One communication topology that solves the broken link issue and can reduce the device-to-device latency is a star topology, where several nodes connect directly to one central host device. Figure 2-2 shows a star topology system with N (N≥2) node devices.

GUID-4590DCC7-4C16-4855-BA55-5E9368DF1061-low.png Figure 2-2 Star Topology Example

The host device's FSI transmitter is connected to the FSI receiver of each node device in order for the host to broadcast data packets to all nodes simultaneously. The node device transmitter's, on the other hand, are connected to independent receivers of the host device enabling them to send data directly back to the host at any time. This star implementation comes with a resource cost as the host needs N number of independent FSI receiver modules. The F2838x family of C2000 devices fit into the host socket with having two FSI transmitters and eight FSI receivers.

 

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