The primary goal of this document is to establish a minimum set of requirements necessary to help assure functional success in new application designs for Texas Instruments high performance multiprocessor DSPs incorporating DDR3 memory interfaces.

Technological advances in memory architecture in both speed and densities for DDR3 require a different mindset when it comes to application implementation and design compared to the customary and traditional SRAM, DDR, and DDR2 devices.

This section is not intended to present a detailed listing of differences between DDR2 and DDR3 designs, but to provide key insight into specific differences that will have a positive impact as customers migrate from a DDR2 to a DDR3 platform (based on the assumption the DDR3 interface is implemented correctly).