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  • LMG1205 100-V, 1.2-A to 5-A, Half Bridge GaN Driver with Integrated Bootstrap Diode

    • SNOSD37B march   2017  – april 2023 LMG1205

      PRODUCTION DATA  

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  • LMG1205 100-V, 1.2-A to 5-A, Half Bridge GaN Driver with Integrated Bootstrap Diode
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output
      2. 7.3.2 Start-up and UVLO
      3. 7.3.3 HS Negative Voltage and Bootstrap Supply Voltage Clamping
      4. 7.3.4 Level Shift
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD Bypass Capacitor
        2. 8.2.2.2 Bootstrap Capacitor
        3. 8.2.2.3 Power Dissipation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
      1.      Mechanical, Packaging, and Orderable Information
  12. IMPORTANT NOTICE
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DATA SHEET

LMG1205 100-V, 1.2-A to 5-A, Half Bridge GaN Driver with Integrated Bootstrap Diode

1 Features

  • Independent high-side and low-side
    TTL logic inputs
  • 1.2-A peak source, 5-A sink current
  • High-side floating bias voltage rail
    operates up to 100 VDC
  • Internal bootstrap supply voltage clamping
  • Split outputs for adjustable
    turnon, turnoff strength
  • 0.6-Ω pulldown, 2.1-Ω pullup resistance
  • Fast propagation times (35 ns typical)
  • Excellent propagation delay matching
    (1.5 ns typical)
  • Supply rail undervoltage lockout
  • Low power consumption

2 Applications

  • Current-fed push-pull converters
  • Half and full-bridge converters
  • Synchronous buck converters
  • Two-switch forward converters
  • Forward with active clamp converters

3 Description

The LMG1205 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck, boost, or half-bridge configuration. The device has an integrated 100-V bootstrap diode and independent inputs for the high-side and low-side outputs for maximum control flexibility. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The inputs of the LMG1205 are TTL logic compatible and can withstand input voltages up to 14 V regardless of the VDD voltage. The LMG1205 has split-gate outputs, providing flexibility to adjust the turnon and turnoff strength independently.

In addition, the strong sink capability of the LMG1205 maintains the gate in the low state, preventing unintended turnon during switching. The LMG1205 can operate up to several MHz. The LMG1205 is available in a 12-pin DSBGA package that offers a compact footprint and minimized package inductance.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMG1205 DSBGA (12) 2.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-94D2485B-D872-4E0F-9D83-08D677C0E590-low.gif Simplified Application Diagram

4 Revision History

Changes from Revision A (February 2018) to Revision B (April 2023)

  • Changed title of data sheet from 80-V to 100-VGo
  • Added clamping circuit delay time and functional explanation to Section 7.3.3 Go
  • Changed equation in Section 8.2.2.2 Go

Changes from Revision * (March 2017) to Revision A (February 2018)

  • Changed title of data sheet Go

 

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