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  • DS90UB921-Q1 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

    • SNLS488 March   2016 DS90UB921-Q1

      PRODUCTION DATA.  

  • CONTENTS
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  • DS90UB921-Q1 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings - JEDEC
    3. 6.3  ESD Ratings—IEC and ISO
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  PCLK Timing Requirements
    9. 6.9  Recommended Timing for the Serial Control Bus
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Charateristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  High Speed Forward Channel Data Transfer
      2. 7.3.2  Low Speed Back Channel Data Transfer
      3. 7.3.3  Common Mode Filter Pin (CMF)
      4. 7.3.4  Video Control Signal Filter
      5. 7.3.5  EMI Reduction Features
        1. 7.3.5.1 Input SSC Tolerance (SSCT)
      6. 7.3.6  LVCMOS VDDIO Option
      7. 7.3.7  Power Down (PDB)
      8. 7.3.8  Remote Auto Power-Down Mode
      9. 7.3.9  Input PCLK Loss Detect
      10. 7.3.10 Serial Link Fault Detect
      11. 7.3.11 Pixel Clock Edge Select (TRFB)
      12. 7.3.12 Frequency Mode Optimizations
      13. 7.3.13 Interrupt Pins - Funtional Description and Usage (INTB, REM_INTB)
      14. 7.3.14 Internal Pattern Generation
      15. 7.3.15 GPIO[3:0] and GPO_REG[7:4]
        1. 7.3.15.1 GPIO[3:0] Enable Sequence
        2. 7.3.15.2 GPO_REG[7:4] Enable Sequence
      16. 7.3.16 I2S Transmitting
      17. 7.3.17 Built In Self Test (BIST)
        1. 7.3.17.1 BIST Configuration and Status
          1. 7.3.17.1.1 Sample BIST Sequence
        2. 7.3.17.2 Forward Channel And Back Channel Error Checking
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Select (MODE_SEL)
      2. 7.4.2 Repeater Application
        1. 7.4.2.1 Repeater Configuration
        2. 7.4.2.2 Repeater Connections
    5. 7.5 Programming
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 AVMUTE Operation
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Up Requirements and PDB Pin
    2. 9.2 CML Interconnect Guidelines
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
  13. IMPORTANT NOTICE
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DATA SHEET

DS90UB921-Q1 5 - 96 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: -40℃ to +105℃ Ambient Operating Temperature Range
    • Device HBM ESD Classification Level ±8kV
    • Device CDM ESD Classification Level C6
  • Supports Extended High Definition (1920x720p/60Hz) Digital Video Format
  • 5 – 96MHz PCLK Supported (STP mode)
  • 15 – 96MHz PCLK Supported (Coax mode)
  • RGB888 + VS, HS, and DE
  • Parallel LVCMOS Video Inputs
  • Spread Spectrum Tolerant Input
  • 4 Optional Bidirectional GPIO Channels
  • Bidirectional Control Interface Channel Interface with I2C Compatible Serial Control Bus
  • Optional I2S Support
  • AC-Coupled Coax or STP Interconnect Up to 10 meters
  • Single 3.3 V Operation with 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
  • DC-Balanced and Scrambled Data with Embedded Clock
  • Internal Pattern Generation
  • Low Power Modes Minimize Power Dissipation
  • >8kV ISO 10605 ESD Rating

2 Applications

  • Automotive Touch Screen Display
  • Automotive Display for Navigation
  • Automotive Instrument Cluster

3 Description

The DS90UB921-Q1 serializer, in conjunction with a DS90UB922-Q1, DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.

The chipset is ideally suited for automotive video-display systems with WVGA and HD formats. The DS90UB921-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single link. Consolidation of video data and control over a single differential pair (or single wire) reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UB921-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential (or single-ended) signaling. Up to 24 data bits are serialized along the video control signals.

EMI is minimized by the use of low voltage swing signaling, data scrambling and randomization and spread spectrum clocking compatibility.

Remote interrupts from the downstream deserializer are mirrored to a local output pin.

Device Information (1)

PART NUMBER PACKAGE BODY SIZE (NOM)
DS90UB921-Q1 WQFN (48) 7.00 mm × 7.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.
DS90UB921-Q1 921-922typapp.gif

4 Revision History

DATE REVISION NOTES
March 2016 * Initial release.

5 Pin Configuration and Functions

DS90UB921-Q1
48 Pin WQFN (RHS)
Top View
DS90UB921-Q1 921pinout.gif

Pin Functions

PIN I/O, TYPE DESCRIPTION
NAME NUMBER
LVCMOS PARALLEL INTERFACE - Layout note: for unused LVCMOS input pins, tie to an external pulldown
DIN[23:18], DIN[15:10], DIN[7:2] / R[7:2], G[7:2], B[7:2] 27, 28, 29, 32, 33, 34, 37, 38, 39, 40, 41, 42, 45, 46, 47, 48, 1, 2 I, LVCMOS, PD Parallel Interface Data Input Pins
DIN[1:0], DIN[9:8], DIN[17:16] / R[1:0], G[1:0], B[1:0] 25, 26, 35, 36, 43, 44 Multi-function pin
I/O, LVCMOS, PD		 Parallel Interface Data Input Pins
DIN0 / R0 can optionally be used as GPIO0 and DIN1 / R1 can optionally be used as GPIO1
DIN8 / G0 can optionally be used as GPIO2 and DIN9 /G1 can optionally be used as GPIO3
DIN16 / B0 can optionally be used as GPO_REG4 and DIN17 / B1 can optionally be used as GPO_REG5
HS 3 I, LVCMOS, PD Horizontal Sync Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Video Control Signal Filter.
VS 4 I, LVCMOS, PD Vertical Sync Input Pin
Video control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130 PCLKs.
See Video Control Signal Filter.
DE 5 I, LVCMOS, PD Data Enable Input Pin
Video control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control Signal Filter is enabled. There is no restriction on the minimum transition pulse when the Control Signal Filter is disabled. The signal is limited to 2 transitions per 130 PCLKs.
See Video Control Signal Filter.
PCLK 10 I, LVCMOS, PD Pixel Clock Input Pin. Strobe edge set by TRFB configuration register. See Table 7 0x03[0].
I2S_CLK, I2S_WC, I2S_DA 13, 12, 11 Multi-function pin
I, LVCMOS, PD		 Digital Audio Interface Data Input Pins
Leave open if unused
I2S_CLK can optionally be used as GPO_REG8, I2S_WC can optionally be used as GPO_REG7, and I2S_DA can optionally be used as GPO_REG6.
OPTIONAL PARALLEL INTERFACE - Layout note: for unused interface pins, tie to an external pulldown
GPIO[3:0] 36, 35, 26, 25 Multi-function pin
I/O, LVCMOS, PD		 General Purpose IOs. Available only in 18-bit color mode, and set by MODE_SEL pin or configuration register. See Table 7 0x0D - 0x0F.
Leave open if unused.
Shared with DIN9, DIN8, DIN1 and DIN0
GPO_REG[7:4] 12, 11, 44, 43 Multi-function pin
O, LVCMOS, PD		 General Purpose Outputs and set by configuration register. See Table 7 0x0F - 0x11.
Share with I2S_WC, I2S_DA, or DIN17, DIN16.
CONTROL
PDB 21 I, LVCMOS, PD Power-down Mode Input Pin
PDB = H, device is enabled (normal operation)
Refer to Power Up Requirements and PDB Pin section.
PDB = L, device is powered down.
When the device is in the powered down state, the Driver Outputs are both HIGH, the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
MODE_SEL 24 S Device Configuration Select. See Table 5.
FSEL 15 I, LVCMOS, PU Frequency Mode Select. Enables Intermediate Frequency mode for coaxial operation. See Frequency Mode Optimizations.
I2C
IDx 6 S I2C Serial Control Bus Device ID Address Select
External pull-up to VDD33 is required under all conditions, DO NOT FLOAT.
Connect to external pull-up and pull-down resistor to create a voltage divider. See Table 6.
SCL 8 I/O, Open Drain I2C Clock Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
SDA 9 I/O, Open Drain I2C Data Input / Output Interface
Must have an external pull-up to VDD33, DO NOT FLOAT.
Recommended pull-up: 4.7kΩ.
STATUS - Layout note: for unused interface pins, leave as No Connect
INTB 31 O, Open Drain Interrupt
INTB = H, normal
INTB = L, Interrupt request
Typically connected with 4.7kΩ to VDDIO.
REM_INTB 16 O, LVCMOS, PD Interrupt. Mirrors status of INTB_IN from the remote deserializer. Note: REM_INTB will be driven LOW until lock is achieved with the downstream deserializer.
REM_INTB = H, normal
REM_INTB = L, interrupt request
FPD-LINK III SERIAL INTERFACE
DOUT+ 20 O, LVDS True Output
The output must be AC-coupled per the typical connection diagram.
DOUT- 19 O, LVDS Inverting Output
The output must be AC-coupled per the typical connection diagram.
CMF 23 CAP Common Mode Filter.
Typically connected with 0.1µF to GND
POWER AND GROUND (1)
VDD33 22 Power Power to on-chip regulator 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND
VDDIO 30 Power LVCMOS I/O Power 1.71 V - 1.89 V OR 3.0 V - 3.6 V. Typically connected with 4.7 uF to GND
GND DAP Ground DAP is the large metal contact at the bottom side, located at the center of the WQFN package. Connect to the ground plane (GND) with at least 9 vias.
REGULATOR CAPACITOR
CAPHS12, CAPP12 17, 14 CAP Decoupling capacitor connection for on-chip regulator. Typically connected with 4.7uF to GND at each CAP pin.
CAPL12 7 CAP Decoupling capacitor connection for on-chip regulator. Typically connected with two 4.7uF to GND at this CAP pin.
OTHERS
RES1 18 GND Reserved. Tie to Ground.
(1) The VDD (VDD33 and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise.

The definitions below define the functionality of the I/O cells for each pin. I/O TYPE:

  • CAP = Capacitor connection
  • LVCMOS = LVCMOS pin; Referenced to VDDIO IO supply
  • I = Input
  • O = Output
  • I/O = Input/Output
  • S = Strap pin. All strap pins have weak internal pull-ups or pull-downs. If the default strap value is needed to be changed then an external resistor should be used.
  • PD, PU = Weak Internal Pull-Down/Pull-Up
  • Multi-function pin

 
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