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  • Splitter Mode Operations With the DS90Ux941AS-Q1

    • SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

       

  • CONTENTS
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  • Splitter Mode Operations With the DS90Ux941AS-Q1
  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History
  14. IMPORTANT NOTICE
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APPLICATION NOTE

Splitter Mode Operations With the DS90Ux941AS-Q1

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

The DS90Ux941AS-Q1 splitter and cropping functions allow system designers to use cost-effective IVI systems with only a single AP for delivering content to two symmetric or asymmetric displays. An application processor can receive and combine two video frames into a superframe, and perform the necessary video data formatting to ensure that the data is compatible with the DS90Ux941AS-Q1 signal processing functions (see Figure 1-1). The DS90Ux941AS-Q1 performs further video formatting and splits of the superframe into two symmetric frames before forwarding them to the compatible FPD-Link III deserializers and attached displays. If necessary, the DS90Ux941AS-Q1 can also crop either one or both resultant frames for the formation of asymmetric frames before forwarding the frames to the deserializers and asymmetric displays.

GUID-FEEBBEC5-F637-4341-9775-6159EBF0B270-low.gifFigure 1-1 Superframe Creation and Splitting System Block Diagram

2 Superframe Requirements

The DS90Ux941AS-Q1 supports superframe options with the following formats:

  • Left/Right 3D format
  • Alternate Line 3D format
  • Alternate Pixel 3D format

For the first two options, the DS90Ux941AS-Q1 reorganizes the superframe into an alternating pixel format for easy splitting at the DS90Ux941AS-Q1 output. For the Alternate Pixel option, the superframe is already in the proper format for splitting.

For proper transition between operating modes, only enable 3D modes when the DSI input is disabled.

 
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