This section provides Failure In Time (FIT) rates for LMT86-Q1 based on two different industry-wide used reliability standard. Table 1-1 provides FIT rates based on IEC TR 62380 / ISO 26262 part 11.

The failure rate and mission profile information in Table 1-1 comes from the Reliability data handbook IEC TR 62380 / ISO 26262 part 11:

• Mission Profile: Motor Control from Table 11
• Power dissipation: 1.0mW
• Climate type: World-wide Table 8
• Package factor lambda 3 Table 17b
• Substrate material: FR4
• EOS FIT rate assumed: 0 FIT

The failure mode distribution estimation for LMT86-Q1 in Table 2-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity, and from best engineering judgments.

The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.

This section provides a failure mode analysis (FMA) for the pins of the LMT86-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

• Pin short-circuited to ground (see Table 3-2)
• Pin open-circuited (see Table 3-3)
• Pin short-circuited to an adjacent pin (see Table 3-4)
• Pin short-circuited to supply (see Table 3-5)

Table 3-2 through Table 3-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 3-1.

Figure 3-1 shows the SC70 package pin diagram. For a detailed description of the device pins, see the Pin Configuration and Functions section in the LMT86-Q1 data sheet.

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

• Bypass capacitor on the input voltage pin of 0.01 µF.
• Series resistors are sized to limit the input currents to the analog inputs to < 5 mA.
• Capacitive loading on output pin is limited to 1100 pF.