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  • LMK5C33216AEVM Evaluation Module

    • SNAU295 July   2024 LMK5C33216A

       

  • CONTENTS
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  • LMK5C33216AEVM Evaluation Module
  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2EVM Quick Start
  6. 3EVM Configuration
    1. 3.1  Power Supply
    2. 3.2  Logic Inputs and Outputs
    3. 3.3  Switching Between I2C and SPI
    4. 3.4  Generating SYSREF Request
    5. 3.5  XO Input
      1. 3.5.1 48MHz TCXO (Default)
      2. 3.5.2 External Clock Input
      3. 3.5.3 Additional XO Input Options
      4. 3.5.4 APLL Reference Options
    6. 3.6  Reference Clock Inputs
    7. 3.7  Clock Outputs
    8. 3.8  Status Outputs and LEDS
    9. 3.9  Requirements for Making Measurements
    10. 3.10 Typical Phase Noise Characteristics
  7. 4EVM Schematics
    1. 4.1  Power Supply Schematic
    2. 4.2  Alternative Power Supply Schematic
    3. 4.3  Power Distribution Schematic
    4. 4.4  LMK5C33216A and Input References IN0 to IN1 Schematic
    5. 4.5  Clock Outputs OUT0 to OUT3 Schematic
    6. 4.6  Clock Outputs OUT4 to OUT9 Schematic
    7. 4.7  Clock Outputs OUT10 to OUT15 Schematic
    8. 4.8  XO Schematic
    9. 4.9  Logic I/O Interfaces Schematic
    10. 4.10 USB2ANY Schematic
  8. 5EVM Bill of Materials
    1. 5.1 Loop Filter and Vibration Nonsensitive Capacitors
  9. 6Appendix A - TICS Pro LMK5B33216 Software
    1. 6.1  Using the Start Page
      1. 6.1.1 Step 1
      2. 6.1.2 Step 2
      3. 6.1.3 Step 3
      4. 6.1.4 Step 4
      5. 6.1.5 Step 5
      6. 6.1.6 Step 6
      7. 6.1.7 Step 7
    2. 6.2  Using the Status Page
    3. 6.3  Using the Input Page
      1. 6.3.1 Cascaded Configurations
        1. 6.3.1.1 Cascade VCO to APLL Reference
    4. 6.4  Using APLL1, APLL2, and APLL3 Pages
      1. 6.4.1 APLL DCO
    5. 6.5  Using the DPLL1, DPLL2, and DPLL3 Pages
      1. 6.5.1 DPLL DCO
    6. 6.6  Using the Validation Page
    7. 6.7  Using the GPIO Page
      1. 6.7.1 SYNC/SYSREF/1-PPS Page
    8. 6.8  Using the Outputs Page
    9. 6.9  EEPROM Page
    10. 6.10 Design Report Page
  10. IMPORTANT NOTICE
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User's Guide

LMK5C33216AEVM Evaluation Module

Abstract

The LMK5C33216AEVM is an evaluation module for the LMK5C33216A Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping.

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

Overview

The LMK5C33216AEVM is an evaluation module for the LMK5C33216A Network Clock Generator and Synchronizer. The EVM can be used for device evaluation, compliance testing, and system prototyping. The LMK5C33216A integrates three Analog PLLs (APLL) and three Digital PLLs (DPLL) with programmable loop bandwidth. The EVM includes SMA connectors for clock inputs, optional off-board APLL reference input, and clock outputs to interface the device with 50Ω test equipment. The onboard TCXO allows the LMK5C33216A to be evaluated in free-running, locked, or holdover mode of operation. The EVM can be configured through the onboard USB microcontroller (MCU) interface using a PC with TI's TICS Pro software graphical user interface (GUI). TICS Pro can be used to program the LMK5C33216A registers.

Features

  • LMK5C33216A

What is Included

  • LMK5C33216AEVM
  • 3-ft. mini-USB cable (MPN 3021003-03)

What is Needed

  • Windows PC with TICS Pro Software GUI
  • Test equipment
    • DC power supply (12V, 1A for EVM Default setting or 5V, 2A for other settings in Table 3-2)

What is Recommended

  • Test equipment:
    • Source signal analyzer
    • Signal generator / reference clock
    • Real-time oscilloscope
    • Precision frequency counter

Figure 1-1 shows the jumper position with red markings. Figure 1-1 shows the DIP switch positions in either green boxes (for ON) or red boxes (for OFF) in the appropriate location.

LMK5C33216AEVM LMK5C33216AEVM Default Setting of Jumpers and DIP Switches Figure 1-1 LMK5C33216AEVM Default Setting of Jumpers and DIP Switches

 
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