This user’s guide describes the evaluation module (EVM) for the TPS25984 eFuse. The TPS25984 device is a 4.5-V to 16-V and 70-A (peak) stackable eFuse with accurate and fast current monitor. This device supports parallel connection of multiple eFuses for higher current designs by actively synchronizing the device states and sharing the loads during start-up and steady-state. The TPS25984 eFuse has an integrated FET with ultra-low ON resistance of 0.8 mΩ, adjustable and robust overcurrent and short-circuit protections, precise load current monitoring, fast overvoltage protection (fixed 16.7-V threshold), adjustable output slew rate control for inrush-current protection, and overtemperature protection to verify FET SOA. The TPS25984 eFuse also has adjustable overcurrent transient blanking timer to support load transients, adjustable undervoltage protection, integrated FET health monitoring and reporting, analog die temperature monitor output, and dedicated fault and power good indication pins.
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The TPS25984EVM eFuse evaluation board allows reference circuit evaluation of Texas Instruments (TI) TPS25984 eFuse. The TPS25984 device is a 4.5-V to 16-V and 70-A (peak) stack-able eFuse with accurate and fast current monitor. This device supports parallel connection of multiple eFuses for higher current designs by actively synchronizing the device states and sharing the loads during start-up and steady-state. The TPS25984 eFuse has an integrated FET with ultra-low ON resistance of 0.8 mΩ, adjustable and robust overcurrent and short-circuit protections, precise load current monitoring, fast overvoltage protection (fixed 16.7-V threshold), adjustable output slew rate control for inrush current protection, and over-temperature protection to verify FET SOA. The TPS25984 eFuse also has adjustable overcurrent transient blanking timer to support load transients, adjustable undervoltage protection, integrated FET health monitoring and reporting, analog die temperature monitor output, and dedicated fault and power good indication pins.
TPS25984EVM comes with two (2) TPS25984 eFuses connected in parallel to evaluate a 12-V (typical) and 110-A (steady-state) design. TPS25984EVM eFuse evaluation board features include:
This EVM can be used on the following applications:
The TPS25984EVM enables the evaluation of TPS259840x and TPS259841x eFuses from TPS25984 family. This EVM has two (2) TPS259840x eFuses connected in parallel. The input power is applied across the connectors T1 and T3, while T2 and T3 provide the output connection for the EVM; refer to the schematic in 2 and EVM test setup in 3. TVS diodes D1 and D2 provide the input protection from transient overvoltages. Schottky diodes D3 and D4 protect the output by clamping the negative voltage excursion at the OUT pins of TPS25984 eFuses within the minimum absolute rating.
SW1 allows to do power cycle and SW2 enables the quick output discharge (QOD). Power Good (PG) and fault (FLTb and FLTb2) indicators are provided by LED DG1, DR1, and DR2 respectively.
EVM Function | VIN UVLO Threshold | VIN OVLO Threshold | ITIMER | Output Slew Rate (dv/dt) | IMON | ILIM | ILIM2 | IREF |
---|---|---|---|---|---|---|---|---|
Performance evaluation of TPS25984, 4.5-V to 16-V, 55-A (RMS) eFuse | 5 V | 16.7 V | Selectable - 1.4 ms and 14 ms | Selectable - 1.2 V/ms, 1.8 V/ms, and 12 V/ms | Selectable - 120 A and 70 A with VREF of 1 V | Selectable - 38 A and 22 A of inrush current limit and 59 A and 35 A of active current sharing threshold with VREF of 1 V | Selectable - 1 V and 0.8 V |
2 illustrates the EVM schematic.
4 lists the TPS25984EVM eFuse Evaluation Board input and output connectors functionalities. Table 4-2 and 6 describe the availability of test points and the functionalities of the jumpers. 5 presents the functions of the signal LEDs.
Connector | Label | Description |
---|---|---|
T1 | VIN (+) | Positive terminal for the input power to the EVM |
T2 | VOUT (+) | Positive terminal for the output power from the EVM |
T3 | PGND (–) | Negative terminal for the EVM (Common for both input and output) |
Test Points | Label | Description |
---|---|---|
TP1 | S1_P | Kelvin sensing points to measure on-resistance: Primary Device (U1) |
TP2 | S1_N | |
TP3 | S2_P | Kelvin sensing points to measure on-resistance: Secondary Device (U2) |
TP4 | S2_N | |
TP5 | VIN | Input Voltage |
TP6 | VOUT | Output Voltage |
TP7 | MODE2 | MODE selection: Secondary Device |
TP8 | FLTb2 | Open-drain active low fault indication: Primary Device |
TP9 | VDD-PRI | Controller input power: Primary Device |
TP10 | FLTb | Open-drain active low fault indication: Primary Device |
TP11 | SWEN | Open-drain signal to indicate and control power switch ON and OFF status |
TP12 | TEMP | Maximum device die temperature monitor analog voltage output with two (2) TPS25984 eFuses in parallel |
TP13 | DVDT | Start-up output slew rate control |
TP14 | ITIMER | Overcurrent blanking timer: Primary Device |
TP15 | IMON | Load current monitor and overcurrent and fast-trip thresholds during steady state |
TP16 | ILIM2 | Current limit and fast-trip threshold during start-up: Secondary Device |
TP17 | ILIM | Current limit and fast-trip threshold during start-up: Primary Device |
TP18 | IREF | Reference voltage for overcurrent and short-circuit protections, and active current sharing blocks |
TP19 | MODE | MODE selection: Primary Device |
TP20 | PG | Open-drain active high power good indication |
TP21 | ITIMER2 | Overcurrent blanking timer: Secondary Device |
TP22 | EN | Active high enable input |
TP23 | VDD-SEC | Controller input power: Secondary Device |
TP24 | VDD PULLUP | 5 V pullup power supply generated using a LDO from VIN |
TP25 | VCC EXTERNAL | External pullup power supply |
TP26 | GD EXTERNAL | External gate signal for custom load transient |
TP27 | PGND | Supply Ground |
QGND1 | QGND | Device Ground |
G1 | QGND | |
G2 | QGND |
Jumper | Label | Description | Default Jumper Position |
---|---|---|---|
J1 | SWEN | 1-2 Position: The SWEN pull-up supply is generated from VIN using a Zener diode (RZ2 populated and RZ3 depopulated) or using a LDO (RZ2 depopulated and RZ3 populated) | 1-2 |
2-3 Position: The SWEN pin is connected to the ITIMER pin of the Primary Device through a 100-kΩ resistor | |||
J2 | DVDT | 1-2 Position sets the output slew rate to 1.8-V/ms | 5-6 |
3-4 Position sets the output slew rate to 12-V/ms | |||
5-6 Position sets the output slew rate to 1.2-V/ms | |||
J3 | ITIMER | 1-2 Position sets the overcurrent blanking timer to 1.4-ms | 3-4 |
3-4 Position sets the overcurrent blanking timer to 14-ms | |||
J4 | IMON | 1-2 Position sets the circuit breaker threshold to 120-A with VIREF of 1-V | 1-2 |
3-4 Position sets the circuit breaker threshold to 70-A with VIREF of 1-V | |||
J5 | ILIM | 1-2 Position sets the inrush current limit to 38-A and the active current sharing threshold to 59-A with VIREF of 1-V: Primary Device | 1-2 |
3-4 Position sets the inrush current limit to 22-A and the active current sharing threshold to 35-A with VIREF of 1-V: Primary Device | |||
J6 | IREF | 1-2 Position sets the reference voltage for overcurrent, short-circuit protection, and active current sharing blocks to 0.8-V | 3-4 |
3-4 Position sets the reference voltage for overcurrent, short-circuit protection, and active current sharing blocks to 1-V | |||
J7 | ILIM2 | 1-2 Position sets the inrush current limit to 38-A and the active current sharing threshold to 59-A with VIREF of 1-V: Secondary Device | 1-2 |
3-4 Position sets the inrush current limit to 22-A and the active current sharing threshold to 35-A with VIREF of 1-V: Secondary Device | |||
J8 | VDD PULL-UP POWER SUPPLY | 1-2 Position provides the VDD pull-up supply from the external power source | 2-3 |
2-3 Position provides the VDD pull-up supply from the onboard 12-V to 5-V LDO | |||
J9 | EXTERNAL GATE SIGNAL | 1-2 Position provides the GATE signal to the MOSFETs (Q4 – Q6) from the onboard mono-shot | 1-2 |
2-3 Position provides the GATE signal to the MOSFETs (Q4 – Q6) from the external signal generator |
LED | Description |
---|---|
DG1 | When ON, indicates that PG is asserted |
DR1 | When ON, indicates that FLTb is asserted |
DR2 | When ON, indicates that FLTb2 is asserted |