This user’s guide describes a power distribution
network (PDN), PDN-0B, between two TPS6594-Q1 devices and either
DRA829V or TDA4VM processor with independent MCU and Main power
rails. This PDN enables board level isolation of the processor MCU
and Main voltage resources as required to leverage the processor
architecture in implementing two desirable end product features:
- MCU
processor acts as independent safety monitor (MCU
Safety Island) over the Main processing resources to
ensure safe system operations.
- MCU
processor maintains minimum system operations (MCU
Only) to significantly reduce processor power
dissipation thereby extending battery life during
stand-by use cases and reducing component
temperature.
This description includes
the following to clarify platform system operation:
- PDN power
resource connections
- PDN
digital control connections
- Primary
and secondary PMIC default NVM contents
- PMIC
sequencing settings to support different PDN power
state transitions for an advanced processor
system
PMIC and processor data manuals describe recommended operation,
electrical characteristics, external components, package details,
register maps, and overall component functionality. In the event of
any inconsistency between any user's guide, application report, or
other referenced material, the data sheet specification is the
definitive source.