How eFuse Ensures Integrated FET Operation in Safe Operating Area

1 Abstract

Applications such as Hot-swap where Power FET is operated in saturation region under high stress, FET safe operating area (SOA) is a major concern for system designers. Designers need to study the FET SOA curve available in the manufacturers data sheet and determine if the FET can handle the power stress without undergoing damage. This application report covers the significance of FET SOA, how the manufacturers derive SOA plot, and how the hot-swaps designers make sure that external FET is operated within specified SOA. Then, the eFuse protection schemes which help to ensure SOA of the integrated FET are discussed and a detailed method of deriving AOA (Allowed Operating Area) plot from the eFuse data sheet is presented. Finally, design recommendations are shared to prevent violation of eFuse abs maximum rating, and to provide long term reliability of eFuse.

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1 Understanding the FET SOA

SOA defines the maximum value of V_DS, I_DS, and time envelope of operation which the device can be expected to operate without getting damaged.

Figure 1-1 Data Sheet SOA of the CSD19536KTT

The entire SOA is made up of five distinct limitations, each of which shape the overall curve, as shown in Figure 1-1, the SOA for TI’s 100 V D2PAK CSD19536KTT.

Four of these limitations can be easily calculated from the known FET parameters – the R_DS(ON) limit, the current limit, the maximum power limit, and the B_VDSS limit.

R_DS(ON) limit is the maximum R_DS(ON) of FET at maximum operating junction temperature.
Current limit is constrained because of maximum rated junction temperature, package capability and other factors. This region can also be called electrical SOA.
For power limit calculation, the temperature rise for a given pulse duration is calculated using transient thermal impedance plot in the FET data sheet. Power profile which gives temperature rise close to the maximum junction temperature decides the boundary of the SOA curve. Power limit region can also be referred as thermal SOA.
B_VDSS limit is the FET breakdown voltage, defined by FET technology and comes under electrical SOA.

The fifth and the most critical region is the thermal instability region, which cannot be determined with formulas, but must be tested. This portion of the SOA, noted by where the curve deviates from the constant power line that necessarily has a slope of -1 on a current vs. voltage log-log scale, indicates where thermal runaway can occur. The steeper the slope, the more prone the FET is to enter into thermal runaway condition at higher operating voltages. This region can also be called electro-thermal SOA as explained in Section 3. To plot thermal instability region there are two methods:

The most accurate method is the measurement method which is followed at TI. Computer-aided test system is used for the measurement. The FET is stressed with a known current and VDS pulse of certain time duration. If the FET survives this pulse then the drain to source current is increased. This process is repeated till the FET fails.
Another method is power limit calculation where the boundary is calculated based on safe junction temperature rise. This method is not an accurate method and does not present true picture of thermal instability region.

After having looked in detail about FET SOA , here are some FET failure modes that can occur on violating SOA.

B_VDSS violation - Causes reverse-biased body-drift diode break down and large amount of current starts to flow between the source and drain due to the avalanche multiplication process.
Power limit violation - On operating FET for higher power than the SOA boundary for a given time causes die junction temperature to cross the safe threshold and FET will damage due to excessive heat.
Current limit violation - Current limit is a function of maximum junction temperature, internal materials and connection between silicon and plastic package. Violating this can cause failure mechanisms such as excessive heating up of die, wire infusion, thermal degradation of molding compound, and electromigration.

Overall, it can be shown that the violation of maximum junction temperature specification of FET causes the FET to fail. Ensuring FET junction temperature is always at a safe level, also helps in ensuring that FET operates in SOA.

2 Ensuring FET SOA in Hot-Swap Design

Since mechanism to limit external FET junction temperature is not present in traditional hot-swap design, external FET SOA operation is made sure by system designer. First, external FET, power limit, and fault timer are selected. The next task for the designer is to verify FET SOA by calculations and do necessary iterations on the power limit and fault timer values. Once the power limit and fault timer are chosen, critical requirement to check is that the FET will stay within its SOA during all the stressful conditions. Please refer to Section 3.1 in the Robust Hot Swap Design application note for step-by-step design procedure and FET SOA verification in a traditional hot-swap design.

For example, during a Hot-Short the circuit breaker trips and the LM5066I re-start into power limit until the timer runs out. In the worst case, the MOSFET’s VDS equal (VINMAX), IDS equal (PLIM / VINMAX) and the stress event lasts for set fault time. The SOA for chosen fault timer duration can be extrapolated by approximating SOA vs time as a power function as shown in Robust Hot Swap Design application note. Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much higher during a hot-short. The SOA has to be de-rated based on case temperature.

The following section describes how eFuse manages SOA of its integrated FET through robust protection mechanisms.