Synchronous buck converter with adaptive constant on-time (D-CAP™) control structure is widely used in various electronic systems, because of its fast transient performance, few external components for low cost and small solution size. In some special applications, it needs the D-CAP™ buck converter to operate in the standby state with pre-bias output and floated input. For previous literature about D-CAP™ structure, most of them focused on normal power transfer operation and loop performance. But the research and the assessment of the pre-bias standby operation has not been involved. Based on the basic logic of the D-CAP™ control, this application note will do a deep analysis and risk assessment about the pre-bias standby operation which has an important meaning in time saving and cost reduction.
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Synchronous buck converter with adaptive constant on-time (D-CAP™) structure [1-2] is widely used as a second-stage source in electronic systems to supply various load, such as MCU, FPGA, and another signal device. In some applications, for the purpose of main source off-line operation, there will exist a backup source (such as battery or super capacitor) to support load after the main power supply being cut off. As shown in Figure 1-1, the Buck converter of main power source will encounter to operate with bias output and floating input. Actually, several of TI’s adaptive on-time control converters already can support normal output pre-bias start up [4-5] with input side clamping to a voltage source. However, because of unclear conception about this special conditional with input floating, there is a common way which uses a controlled switch to avoid power flow back to input of Buck converter. But it will increase the cost and the size of the system. Based on the buck converters with the normal pre-bias start up function, this paper will make a deep analysis of the floating-input pre-bias output operation and assess the feasibility of removing the controlled switch for cost saving purpose.
From the topology of Buck converter shown in Figure 1-1, it can be seen as that output is clamped by a bias voltage source Vbias. Because of the existing of body diode of MOSFET, the input voltage Vin will be clamped by Vbias through the body diode of the high side MOSFET, initially. Input voltage is shown in Equation 1. Actually, most of TI's IC has two basic functions : Enable function and UVLO (under voltage lock out). Device will shut down, if input voltage is lower than UVLO threshold or logic level at Enable pin is ineffective. If Vbias is a low voltage which can cause Vin to be lower than the UVLO threshold, it is obvious that the device will not start up.
If Vin is higher than UVLO threshold and Enable pin is logic effective, the device will start up and implement its logic. In this case, there’s another way that use a controlled signal to let Enable pin be ineffective, which can avoid the converter to operate to make sure there is no continuous energy flow into input side . But it will need more external components to achieve that or occupy more digital I/O resource if MCU is used.
This application note's discussion focuses on the situation Vbias-Vdiode>VUVLO and Enable pin directly being enabled from Vin. Generally, D-CAP™ structure device can be divided to two types. One type is the PSM (pulse-skip mode) device. PSM device has the logic ZC (zero-cross) detection and will reduce its frequency in light-load condition, which can implement a better light-load efficiency. ZC logic will monitor the inductor current during the low-side MOSFET turn on time, if the inductor current trend to be lower than zero, the low side MOSFET will turn off. It means that the inductor current will not be negative, if ZC logic is implemented. Another is the FCCM (force continuous conductive mode) device without the ZC, which implement a constant steady-state frequency under all load conditions. Because different types device can cause different behaviors, this application note will discuss the operation of PSM and FCCM mode device separately.