The TPS560430 regulator is an easy-to-use synchronous step-down DC/DC converter operating from 4-V to 36-V supply voltage. It is capable of delivering up to 600-mA DC load current in a very small solution size. The family has different versions applicable for different applications, 1.1-MHz and 2.1-MHz switching frequency, PFM and FPWM, adjustable and fixed output voltage. The device is suitable for a wide range of applications from industrial to automotive for power conditioning from an unregulated source. The TPS560430 employs peak-current mode control with internal loop compensation, which reduces design time, and requires few external components.

A lot of PCM loop models are available for system design. The most popular model is provided in [2]. The model predicted the sample and hold effects in the current loop, while using a three-terminal switch model to calculate power stage small signal model. Using this method, a simplified loop model is provided in [3], and an equivalent circuit is obtained to simulate the loop response. However, if all of the models require simulation tools to draw the bode plot, then find a crossover frequency and phase margin based on the bode plot. Besides, the transfer function of inner current loop is quite complex, making it hard to understand how it impacts the whole loop response. In this document, a simple equation is provided to calculate bandwidth. The phase margin is obtained by simplifying the inside current loop as a single pole. The inner current loop stability criteria can be obtained based on the model. Each zero and pole in the model has a clear physical meaning, making it easy to analyze the impact of each component value on the loop response. The inductor and output capacitor design procedure of the internally compensated PCM buck converter is given using the model. The model accuracy is verified by both simulation and bench measurement results.

Figure 2-1 shows the simplified schematic for the PCM buck converter.

Figure 2-1 Simplified Schematic for PCM Buck Converter

Figure 2-2 Overall Control Implementation

Figure 2-2 shows the overall control block model where:

• G_di(s) is the duty cycle to i_L transfer function.
• Z_O(s) is the transfer function of output impedance.
• G_div(s) is the gain of the feedback resistor network.
• G_EA(s) is the transfer function of the error amplifier with certain compensation.
• F_m is the gain of PCM PWM comparator.
• R_i is the current sensing resistor.
• H_e(s) is the transfer function model of inductor current sampling-hold effect.

Equation 1 shows the transfer function from the inductor current to the output voltage.

Equation 1.

G_di(s) is the duty cycle to i_L transfer function.

Equation 2.

The internal loop compensation is designed so that the crossover frequency is much higher than the corner frequency, 1/(2π√LC_O). For crossover frequency and higher frequency, Equation 2 can be simplified as Equation 3.

Equation 3.

The sensed inductor current, external ramp, and the output of error amplifier V_COMP are compared, which determines when to turn off the high side MOSFET, hence the duty cycle is determined. F_m is the comparator gain. f_SW is the switching frequency. S_n is the on-time slope of the sensed-current waveform and S_e is the external ramp slope.

Equation 4.

where

H_e(s) is the transfer function model of inductor current sampling-hold effect. [2]2:

Equation 5.

Equation 6 shows the transfer function of the feedback.

Equation 6.

Equation 7 shows the transfer function of the error amplifier with certain compensation.

Equation 7.