Figure 1-1 highlights the user interface items associated with the EVM. The VIN and PGND terminal blocks (J1 and J3) are used for connection to the host input supply and the VOUT and PGND terminal blocks (J4, J10, J13, J16) are used for connection to the load. These terminal blocks can accept up to 16-AWG wire.

Figure 1-1 EVM User Interface

• The VIN S+ and VIN S- input voltage test points as well as the VOUT S+ and VOUT S- output voltage test points, located near the power terminal blocks are intended to be used as voltage monitoring points where voltmeters can be connected to measure VIN and VOUT. Do not use these S+ and S- monitoring test points as the input supply or output load connection points. The PCB traces connecting to these test points are not designed to support high currents.
• The VOUT1 (J2), VOUT2 (J9) and VOUT3 (J14) scope sockets can be used to monitor VOUT waveforms with an oscilloscope. These test points are intended for use with un-hooded scope probes outfitted with a low-inductance ground lead (ground spring) mounted to the scope probe barrel. The two sockets of each test point are on 0.1 inch centers. The scope probe tip should be inserted into the socket marked with a white dot printed on the board and the scope ground lead should be inserted into the other socket.
• The control test points located around the device are made available to test the features of the device. Refer to Section 2 for more information on the individual control test points.
• The VOUT jumpers (J6, J11, J18) and F_SW jumpers (J12, J19) are provided to select the desired output voltage and appropriate switching frequency. The Fsw/SYNC jumpers (J7, J17) are provided to select the desired switching frequency method, either to an external clock (SYNC) or the switching frequency (Fsw) selected by the F_SW jumpers. Before applying power to the EVM, make sure that the jumpers are present and properly positioned for the intended output voltage. Always remove input power before changing the jumper settings.

Wire-loop test points and scope probe sockets are included for digital voltmeters (DVM) or oscilloscope probes to aid in the evaluation of the device. A description of each test point follows:

Figure 3-1 through Figure 3-8 show the PCB layers of the TPSM5D1806EVM.

Figure 3-1 Topside Component View (Top View)

Figure 3-2 Layer 1 (Top View)

Figure 3-3 Layer 2 (Top View)

Figure 3-4 Layer 3 (Top View)

Figure 3-5 Layer 4 (Top View)

Figure 3-6 Layer 5 (Top View)

Figure 3-7 Layer 6 (Top View)

Figure 3-8 Bottom-Side Component Layout (Bottom View)

Figure 4-1 is the schematic for the top-half of TPSM5D1806EVM.

Figure 4-1 TPSM5D1806EVM Independent Dual Output Schematic

Figure 4-2 is the schematic for the bottom-half of TPSM5D1806EVM.

Figure 4-2 TPSM5D1806EVM Independent Parallel Output Schematic

Table 5-1 lists the EVM BOM.