• Menu
  • Product
  • Email
  • PDF
  • Order now
  • UCC28056 System Bring Up Guidelines and Application Debug FAQs

    • SLUAAH3 October   2021 UCC28056

       

  • CONTENTS
  • SEARCH
  • UCC28056 System Bring Up Guidelines and Application Debug FAQs
  1.   Trademarks
  2. 1How to Select the Correct Devices Version of UCC28056 Families?
  3. 2How to Complete the Schematic Review of the UCC28056?
    1. 2.1 VOSNS Pin
    2. 2.2 ZCD/CS Pin
    3. 2.3 DRV Pin
    4. 2.4 GND Pin
    5. 2.5 VCC Pin
    6. 2.6 COMP Pin
  4. 3How to Test and Confirm the UCC28056 Working Mode?
    1. 3.1 How to Capture the ZCD/CS Waveform?
    2. 3.2 How to Evaluate UCC28056 Normal Operation Mode Waveform?
  5. 4Protections and how to Identify Them?
    1. 4.1 OVP1
    2. 4.2 OVP2
    3. 4.3 OCP1
    4. 4.4 OCP2
  6. 5Application Debug Frequently Asked Questions (FAQs).
    1. 5.1  How is the UCC28056 GND Pin Connected?
    2. 5.2  There is CCM Inductor Current During Start-Up, is This a Normal Phenomenon?
    3. 5.3  How to Fine-Tune the RC Parameter on the ZCD/CS Pin?
    4. 5.4  Is it Possible to Increase the High Voltage Cap Value on the ZCD Cap Divider?
    5. 5.5  How to Separate the TONMAX Limit or OCP Protection When the PFC Output Voltage Cannot Follow the Regulated Voltage?
    6. 5.6  Does UCC28056 Support DC Input Application?
    7. 5.7  How Does RDG Change the Delay Time for Valley Switching Detection of the MOSFET?
    8. 5.8  Can UCC28056 Meet Harmonic Performance?
    9. 5.9  Does UCC28056 Have Soft Start?
    10. 5.10 Does the UCC28056 Support Auxiliary-Winding PFC Inductor Input on the ZCD Pin?
  7. 6References
  8. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

APPLICATION NOTE

UCC28056 System Bring Up Guidelines and Application Debug FAQs

Trademarks

All trademarks are the property of their respective owners.

1 How to Select the Correct Devices Version of UCC28056 Families?

Table 1-1 Device Comparison Table
DeviceUCC28056AUCC28056BUCC28056C
Where UsedPFC Output > 400 VApplication With Minimal Audible NoiseGeneral Purpose
Overvoltage Protection Threshold108% VOUT110% VOUT110% VOUT
Second Tier Overvoltage Protection Enabled✓✓
Burst Mode Threshold< 15% Load< 15% Load< 10% Load

The UCC28056 families integrate the Zero Current Detection (ZCD) and the Current Sense (CS) feature together at the ZCD/CS pin, to reduce the package size. This makes the devices cost-competitive in of the smallest packages available. The device layout is designed for both precise detection of drain-to-source voltage and OCP signal sampling. The UCC28056A, UCC28056B, and UCC28056C have improved the noise immunity on the ZCD pin making the controller more robust and less sensitive to noise from downstream.

Table 1-1 shows the key differences of each version. The UCC28056A removes the OVP2 feature. Use this device in applications with wider input voltage range and high output voltage. TI also recommends using the device in applications that are not allowed any restart event during surge or lighting test.

The UCC28056C has a lower burst mode threshold compared with the UCC28056A and UCC28056B. Use the UCC28056C in applications that need lower burst mode power.

The minimum frequency for UCC28056C is around 18 kHz to 20 kHz, and UCC28056A, UCC28056B minimum frequency can be higher than 20 kHz. For some applications that detect the audible noise through audible noise test equipment and scan the frequency from 20 Hz to 20 kHz, select the UCC28056A or UCC28056B version.

For more information about the differences of each version, see the UCC28056 Selection Guide application brief.

2 How to Complete the Schematic Review of the UCC28056?


GUID-20210924-SS0I-9P3W-0QF2-7MM8H5CN59ZQ-low.gif

Figure 2-1 UCC28056 Simplified Application

Review the UCC28056 schematic using the simplified application in Figure 2-1 and check each pin of the controller.

2.1 VOSNS Pin

The VOSNS pin voltage is applied to the inverting input of an internal transconductance error amplifier. The output voltage regulation set point (VOutReg) is determined by the external resistor divider network connecting the output voltage to the VOSNS pin. To ensure that the VOSNS pin bias current degrades output voltage regulation by less than 1%, the upper voltage divider resistor value must be less than 39 MΩ. Although it is possible to increase the divider resistance to reduce the standby power, there is some impact on the output voltage regulation accuracy across parts and temperature, so design the total voltage divider resistance to be around 10 MΩ. The capacitance on the VOSNS pin helps to filter the switching noise and use SMD capacitance with a value of less than 3.3 nF. A higher value may increase the PFC output voltage loop response time.

 

Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale