Stability Analysis and Design of Internally-Compensated Peak Current Mode TPS62933 - Part I: How to Select the Output Capacitor

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1 Introduction

Peak current mode control is widely used in buck controllers and converters due to its advantages for good dynamic performance and easy compensation. Most peak current mode converters have a COMP pin and customers can implement type 2 or type 3 external compensation by adjusting external resistors and capacitors. In recent years, internal compensation attracts more and more attention to reduce solution size and achieve simple application design. The TPS62933 is a buck converter with an internally compensated peak current mode that supports 3.8- to 30-V input voltage and maximum 3-A output current. The device has superior features like low I_Q and a wide output voltage range. Compared to the conventional PCM devices, it does not need external resistors or capacitors for compensation setting, but the stability restriction limits the range of inductance and output capacitance.

For common applications, components can be selected based on the recommended table and implement fast design for application. For special application design to choose large output capacitance or small output capacitance, a stability design method is proposed in this application report. The application with a feedforward capacitor is not included in the analysis.

2 Loop Response of Peak Current Mode Converter

Figure 2-1 shows the schematic of a PCM buck converter. A type 2 compensation is used to ensure the stability of the converter.

Figure 2-1 Simplified Schematic of PCM Buck Converter

The loop response model of PCM buck converters is introduced in the application report⁽²⁾. Figure 2-2 shows the bode plot.

Figure 2-2 Bode Plot of PCM Buck Converter Open Loop Response

In the loop response of PCM converters, the DC gain is affected by output current.

f_{P1_EA}, f_{P2_EA} and f_{Z_EA} are the frequencies of poles and zero generated by the type2 compensation
f_{P1_EA} is the initial pole at low frequency to boost DC gain for improving output voltage accuracy
f_{Z_EA} is a zero to enlarge bandwidth and boost phase margin
f_{P2_EA} is a high-frequency pole to increase gain margin and attenuate high frequency noise

In TPS62933, the DC gain, f_{P1_EA}, f_{P2_EA}, and f_{Z_EA} are all determined by the device internal compensation circuit, which is expressed as Equation 1 and Equation 2.

Equation 1.

where

I_OUT is the output current of the converter

Equation 2.

f_{Z_OUT} and f_{P_OUT} are zero and pole introduced by the output capacitor and load

For the application with all MLCC or small ESR output capacitors, f_{Z_OUT} is at high-frequency range and has limited effects on converter stability.

Equation 3.

Equation 4.

where

C_O is the output capacitance
R_ESR is the ESR of output capacitors
R_O is the output resistor, which equals to V_OUT / I_OUT.

f_{P_ci} is a pole introduced by the inside current loop and related with device slope compensation. Its expression for TPS62933 is shown as Equation 5.

Equation 5.

3 Output Capacitance Upper Limit for Internally-Compensated PCM Buck Converter

Limits for –20 dB/dec at gain crossover frequency
For system loop stability, a –20 dB/dec slope near crossover frequency is ideal for loop gain, since that can normally bring sufficient phase margin⁽³⁾.
Figure 2-2 shows the loop gain slope of the PCM converter changes from 0 to –20 dB/dec at the initial pole frequency, f_{P1_EA}. At pole f_{P_OUT}, the loop gain slope changes to –40 dB/dec. With the compensation of zero f_{Z_EA}, the gain slope becomes –20 dB/dec and the gain curve crosses 0 dB with this slope. That could bring sufficient phase margin for the converter.
Figure 3-1 (a) illustrates that the converter crossover frequency f_c becomes lower with reduced pole frequency f_{P_OUT}. If f_c < f_{Z_EA}, the zero f_{Z_EA} is out of crossover frequency and loop gain crosses 0 dB with a –40 dB/dec slope. If these conditions occur, they may cause insufficient phase margin.
Figure 3-1 Loop Gain of TPS62933 Converter With Zero f_{Z_EA} (a) Out of Bandwidth (b) Inside Bandwidth
Equation 4 shows that pole f_{P_OUT} is inversely related with output capacitance C_O. Reducing C_O can make both f_{P_OUT} and f_c increase. As shown in Figure 3-1 (b), after increasing the pole frequency f_{P_OUT}, f_{Z_EA} could be smaller than the crossover frequency f_c and the loop gain crosses 0 dB with a –20 dB/dec slope. These conditions could normally ensure converter phase margin.
Based on the previous analysis, use Equation 6 to calculate the limitation for –20 dB/dec slope at gain crossover frequency:
Equation 6.
As Equation 2 shows, f_{Z_EA} is fixed at 10.6 kHz for TPS62933. To get the relation between output capacitance C_o and f_c, first calculate the relation between gain and frequency using Equation 7 and Equation 8.
Equation 7.
Equation 8.
where
- A_{P_OUT} is the loop gain at frequency f_{P_OUT}
Equation 7 and Equation 8 can be simplified as:
Equation 9.
Equation 10.
With Equation 4, Equation 6, and Equation 10, the upper limit for output capacitance is calculated using Equation 11.
Equation 11.
Substituting parameters in Equation 1 and Equation 2, the upper limit for TPS62933 is:
Equation 12.
Limits for 45 degree phase margin
Normally for a buck converter, a 45 degree phase margin can be achieved with –20 dB/dec slope at gain crossover frequency. But for a buck regulator with peak current-mode control, when a larger inductance is used, the frequency of the inner current loop pole f_{P_ci} will be lower and bring more phase drop at the gain crossover frequency. These conditions may cause a phase margin lower than 45 degrees, even with –20 dB/dec crossing. Therefore, the capacitance upper limit for a 45 degree phase margin is also deducted in this section.
Figure 3-2 is a bode plot of a PCM buck converter with –20 dB/dec crossing. f_{Z_OUT} and f_{P2_EA} are normally at very high frequency so their effects on phase margin at gain crossover frequency can be ignored at first. Pole f_{P1_EA} is at a very low frequency and brings about –90° phase drop at gain crossover frequency.
Figure 3-2 Bode Plot of PCM Buck Converter Open Loop Response
Next, calculate the phase margin using Equation 13. Equation 14 constitutes the limitation to make the phase margin larger than 45 degrees.
Equation 13.
Equation 14.
Calculate gain crossover frequency f_cross using Equation 15, Equation 16 and Equation 17, based on Figure 3-2.
Equation 15.
Equation 16.
Equation 17.
Derive f_cross using equation Equation 18:
Equation 18.
Substituting Equation 1, Equation 2, and Equation 4 into Equation 18, f_cross is expressed with:
Equation 19.
Substituting Equation 2, Equation 4, Equation 5, and Equation 19 into Equation 14 and ignoring ESR impacts, the upper limit for output capacitance for phase margin restriction is calculated using the following example equation:
```
(50*(111936*IOUT - 4460544))/(441013* IOUT *VOUT*(422400/ IOUT + (8954880000/ IOUT + 178421760000/ IOUT ^2 + (2500* VIN ^2* fsw ^2)/(24649*(4356000*L + VIN - 2* VOUT)^2) - (3180000* VIN *fsw)/(157*(4356000*L + VIN - 2* VOUT)) + (84480000* VIN * fsw)/(157* IOUT *(4356000*L + VIN - 2* VOUT)) - (267632640000* VIN * fsw)/(8321* IOUT ^2*(4356000*L + VIN - 2* VOUT)) + (10560000* VIN ^2* fsw ^2)/(1306397* IOUT *(4356000*L + VIN - 2* VOUT)^2) + (11151360000* VIN ^2* fsw ^2)/(69239041* IOUT ^2*(4356000*L + VIN - 2* VOUT)^2) + 112360000)^(1/2) - (50* VIN * fsw)/(157*(4356000*L + VIN - 2* VOUT)) - (105600* VIN * fsw)/(8321* IOUT *(4356000*L + VIN - 2* VOUT)) + 10600))
```
Since the expression for output capacitance upper limit with phase margin restriction is very complicated, an example of how to use Microsoft® Excel® or MATLAB® for the calculation is introduced in Section A.